dec_copy.map.qmsg

以C语言和Java语言、嵌入式开发、算法实现为主

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 12 15:08:43 2006 " "Info: Processing started: Thu Oct 12 15:08:43 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dec_copy -c dec_copy " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dec_copy -c dec_copy" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "dec_copy.bdf 1 1 " "Warning: Using design file dec_copy.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 dec_copy " "Info: Found entity 1: dec_copy" {  } { { "dec_copy.bdf" "" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dec_copy " "Info: Elaborating entity \"dec_copy\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "output_design.vhd 2 1 " "Warning: Using design file output_design.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 output_design-a " "Info: Found design unit 1: output_design-a" {  } { { "output_design.vhd" "" { Text "E:/My viterbi/viterbi213/output_design.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 output_design " "Info: Found entity 1: output_design" {  } { { "output_design.vhd" "" { Text "E:/My viterbi/viterbi213/output_design.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "output_design output_design:inst1 " "Info: Elaborating entity \"output_design\" for hierarchy \"output_design:inst1\"" {  } { { "dec_copy.bdf" "inst1" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 512 1696 1816 640 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "reg_exchange.vhd 2 1 " "Warning: Using design file reg_exchange.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg_exchange-a " "Info: Found design unit 1: reg_exchange-a" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 32 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 reg_exchange " "Info: Found entity 1: reg_exchange" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_exchange reg_exchange:inst " "Info: Elaborating entity \"reg_exchange\" for hierarchy \"reg_exchange:inst\"" {  } { { "dec_copy.bdf" "inst" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 280 1400 1560 504 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ACS_0.vhd 2 1 " "Warning: Using design file ACS_0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ACS_0-a " "Info: Found design unit 1: ACS_0-a" {  } { { "ACS_0.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_0.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ACS_0 " "Info: Found entity 1: ACS_0" {  } { { "ACS_0.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_0.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ACS_0 ACS_0:inst3 " "Info: Elaborating entity \"ACS_0\" for hierarchy \"ACS_0:inst3\"" {  } { { "dec_copy.bdf" "inst3" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 168 904 1064 296 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ACS_2.vhd 2 1 " "Warning: Using design file ACS_2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ACS_2-a " "Info: Found design unit 1: ACS_2-a" {  } { { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ACS_2 " "Info: Found entity 1: ACS_2" {  } { { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ACS_2 ACS_2:inst5 " "Info: Elaborating entity \"ACS_2\" for hierarchy \"ACS_2:inst5\"" {  } { { "dec_copy.bdf" "inst5" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 496 904 1064 624 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ACS_1.vhd 2 1 " "Warning: Using design file ACS_1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ACS_1-a " "Info: Found design unit 1: ACS_1-a" {  } { { "ACS_1.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_1.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ACS_1 " "Info: Found entity 1: ACS_1" {  } { { "ACS_1.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_1.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ACS_1 ACS_1:inst4 " "Info: Elaborating entity \"ACS_1\" for hierarchy \"ACS_1:inst4\"" {  } { { "dec_copy.bdf" "inst4" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 328 904 1064 456 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ACS_3.vhd 2 1 " "Warning: Using design file ACS_3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ACS_3-a " "Info: Found design unit 1: ACS_3-a" {  } { { "ACS_3.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_3.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ACS_3 " "Info: Found entity 1: ACS_3" {  } { { "ACS_3.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_3.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ACS_3 ACS_3:inst6 " "Info: Elaborating entity \"ACS_3\" for hierarchy \"ACS_3:inst6\"" {  } { { "dec_copy.bdf" "inst6" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 656 904 1064 784 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst\|w2\[0\] data_in GND " "Warning: Reduced register \"reg_exchange:inst\|w2\[0\]\" with stuck data_in port to stuck value GND" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst\|w0\[0\] data_in GND " "Warning: Reduced register \"reg_exchange:inst\|w0\[0\]\" with stuck data_in port to stuck value GND" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst\|w1\[1\] data_in GND " "Warning: Reduced register \"reg_exchange:inst\|w1\[1\]\" with stuck data_in port to stuck value GND" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "reg_exchange:inst\|w0\[1\] data_in GND " "Warning: Reduced register \"reg_exchange:inst\|w0\[1\]\" with stuck data_in port to stuck value GND" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "reg_exchange:inst\|w1\[0\] reg_exchange:inst\|w3\[0\] " "Info: Duplicate register \"reg_exchange:inst\|w1\[0\]\" merged to single register \"reg_exchange:inst\|w3\[0\]\"" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "reg_exchange:inst\|w2\[1\] reg_exchange:inst\|w3\[1\] " "Info: Duplicate register \"reg_exchange:inst\|w2\[1\]\" merged to single register \"reg_exchange:inst\|w3\[1\]\"" {  } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "164 " "Info: Implemented 164 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "25 " "Info: Implemented 25 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "135 " "Info: Implemented 135 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 12 15:08:55 2006 " "Info: Processing ended: Thu Oct 12 15:08:55 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}