uda1341_driver.c

uda1341的驱动,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

     return smdk2410_mixer_ioctl(inode, file, cmd, arg);
 }
 return 0;
}
/***************************************************************************
**
**
***************************************************************************/
static int smdk2410_audio_open(struct inode *inode, struct file *file)
{
 int cold = !audio_active;
 DPRINTK("audio_open\n");
 if ((file->f_flags & O_ACCMODE) == O_RDONLY)
 {
  if (audio_rd_refcount || audio_wr_refcount)
   return -EBUSY;
  audio_rd_refcount++;
 }
 else if ((file->f_flags & O_ACCMODE) == O_WRONLY)
 {
  if (audio_wr_refcount)
   return -EBUSY;
  audio_wr_refcount++;
 }
 else if ((file->f_flags & O_ACCMODE) == O_RDWR)
 {
  if (audio_rd_refcount || audio_wr_refcount)
   return -EBUSY;
  audio_rd_refcount++;
  audio_wr_refcount++;
 }
 else
  return -EINVAL;
 if (cold)
 {
  audio_rate = AUDIO_RATE_DEFAULT;
  audio_channels = AUDIO_CHANNELS_DEFAULT;
  audio_fragsize = AUDIO_FRAGSIZE_DEFAULT;
  audio_nbfrags = AUDIO_NBFRAGS_DEFAULT;
  //by threewater 2003-12-8
  if ((file->f_mode & (FMODE_WRITE|FMODE_READ))==(FMODE_WRITE|FMODE_READ))
  {
   init_s3c2410_iis_bus_rxtx();
   audio_clear_buf(&output_stream);
   audio_clear_buf(&input_stream);
   DPRINTK("sounddev open write and read: by threewater\n");
  }
  else if ((file->f_mode & FMODE_WRITE))
  {
   init_s3c2410_iis_bus_tx();
   audio_clear_buf(&output_stream);
   DPRINTK("sounddev open write: by threewater\n");
  }
  else if ((file->f_mode & FMODE_READ))
  {
   init_s3c2410_iis_bus_rx();
   audio_clear_buf(&input_stream);
   DPRINTK("sounddev open read: by threewater\n");
  }
 }
 MOD_INC_USE_COUNT;
 return 0;
}
/***************************************************************************
**
**
***************************************************************************/

static int smdk2410_mixer_open(struct inode *inode, struct file *file)
{
 MOD_INC_USE_COUNT;
 return 0;
}
/***************************************************************************
**
**
***************************************************************************/

static int smdk2410_audio_release(struct inode *inode, struct file *file)
{
 DPRINTK("audio_release\n");
 if (file->f_mode & FMODE_READ) {
     if (audio_rd_refcount == 1)
    audio_clear_buf(&input_stream);
      audio_rd_refcount = 0;
 }
 if(file->f_mode & FMODE_WRITE) {
     if (audio_wr_refcount == 1) {
        audio_sync(file);
        audio_clear_buf(&output_stream);
        audio_wr_refcount = 0;
       }
    }
 MOD_DEC_USE_COUNT;
 return 0;
}
/***************************************************************************
**
**
***************************************************************************/
static int smdk2410_mixer_release(struct inode *inode, struct file *file)
{
 MOD_DEC_USE_COUNT;
 return 0;
}
/***************************************************************************
**
**
***************************************************************************/

static struct file_operations smdk2410_audio_fops = {
 llseek:  smdk2410_audio_llseek,
 write:  smdk2410_audio_write,
 read:  smdk2410_audio_read,
 poll:  smdk2410_audio_poll,
 ioctl:  smdk2410_audio_ioctl,
 open:  smdk2410_audio_open,
 release: smdk2410_audio_release
};
/***************************************************************************
**
**
***************************************************************************/
static struct file_operations smdk2410_mixer_fops = {
 ioctl:  smdk2410_mixer_ioctl,
 open:  smdk2410_mixer_open,
 release: smdk2410_mixer_release
};
/***************************************************************************
**
**
***************************************************************************/
static void init_uda1341(void)  ///zhaoning
{
 int flags;
   uda1341_volume = 62 - ((DEF_VOLUME * 61) / 100);
 uda1341_boost = 0;
   uda_sampling = DATA2_DEEMP_NONE | DATA2_PEAKAFTER;
 uda_sampling &= ~(DATA2_MUTE);
 
 local_irq_save(flags);
 
 write_gpio_bit(GPIO_L3CLOCK, 1);
 write_gpio_bit(GPIO_L3MODE, 1);
 
 local_irq_restore(flags);
 
 uda1341_l3_address(UDA1341_REG_STATUS);
    uda1341_l3_data(STAT0_RST);
   
 uda1341_l3_address(UDA1341_REG_STATUS);
    uda1341_l3_data(STAT0_SC_384FS | STAT0_IF_MSB | STAT0_DC_FILTER);     // set 384 system clock, MSB
    uda1341_l3_data(STAT1 | STAT1_DAC_GAIN | STAT1_ADC_GAIN | STAT1_ADC_ON | STAT1_DAC_ON);
    uda1341_l3_address(UDA1341_REG_DATA0);
 uda1341_l3_data(DATA0 |DATA0_VOLUME(uda1341_volume));  // maximum volume
 uda1341_l3_data(DATA1 |DATA1_BASS(uda1341_boost)| DATA1_TREBLE(0));
    uda1341_l3_data(DATA2 |uda_sampling); /* --;;*/
 uda1341_l3_data(EXTADDR(EXT2));
 //uda1341_l3_data(EXTDATA(EXT2_MIC_GAIN(0x6)) | EXT2_MIXMODE_CH1);
 uda1341_l3_data(EXTDATA(EXT2_MIC_GAIN(0x6)| EXT2_MIXMODE_CH2));
 uda1341_l3_data(EXTADDR(EXT5));
 uda1341_l3_data(EXTDATA(0x7));
 local_irq_save(flags);
 write_gpio_bit(GPIO_L3CLOCK, 1);
 write_gpio_bit(GPIO_L3MODE, 0);
 local_irq_restore(flags);
}
/***************************************************************************
**
**
***************************************************************************/
static void init_s3c2410_iis_bus_rx(void){
 
 IISCON = 0;
        IISMOD = 0;
        IISFIFOC = 0;

        /* 44 KHz , 384fs */
        IISPSR = (IISPSR_A(iispsr_value(S_CLOCK_FREQ, 44100))
                | IISPSR_B(iispsr_value(S_CLOCK_FREQ, 44100)));
        IISCON = (IISCON_RX_DMA         /* Transmit DMA service request */
                |IISCON_TX_IDLE         /* Receive Channel idle */
                |IISCON_PRESCALE);      /* IIS Prescaler Enable */
        IISMOD = (IISMOD_SEL_MA         /* Master mode */
                | IISMOD_SEL_RX         /* Transmit */
                | IISMOD_CH_RIGHT       /* Low for left channel */
                | IISMOD_FMT_MSB        /* MSB-justified format */
                | IISMOD_BIT_16         /* Serial data bit/channel is 16 bit */
                | IISMOD_FREQ_384       /* Master clock freq = 384 fs */
                | IISMOD_SFREQ_32);     /* 32 fs */
        IISFIFOC = (IISFCON_RX_DMA      /* Transmit FIFO access mode: DMA */
               );       /* Transmit FIFO enable */
        IISCON |= IISCON_EN;            /* IIS enable(start) */
}
/***************************************************************************
**
**
***************************************************************************/
static void init_s3c2410_iis_bus_tx(void)
{
        IISCON = 0;
        IISMOD = 0;
        IISFIFOC = 0;

     /* 44 KHz , 384fs */
 IISPSR = (IISPSR_A(iispsr_value(S_CLOCK_FREQ, 44100))
  | IISPSR_B(iispsr_value(S_CLOCK_FREQ, 44100)));
 IISCON = (IISCON_TX_DMA  /* Transmit DMA service request */
    |IISCON_RX_IDLE  /* Receive Channel idle */
  |IISCON_PRESCALE); /* IIS Prescaler Enable */
  IISMOD = (IISMOD_SEL_MA         /* Master mode */
    | IISMOD_SEL_TX         /* Transmit */
  | IISMOD_CH_RIGHT       /* Low for left channel */
  | IISMOD_FMT_MSB        /* MSB-justified format */
  | IISMOD_BIT_16         /* Serial data bit/channel is 16 bit */
  | IISMOD_FREQ_384       /* Master clock freq = 384 fs */
  | IISMOD_SFREQ_32);     /* 32 fs */
 IISFIFOC = (IISFCON_TX_DMA      /* Transmit FIFO access mode: DMA */
  | IISFCON_TX_EN);       /* Transmit FIFO enable */
 IISCON |= IISCON_EN;  /* IIS enable(start) */
}
/***************************************************************************
**
**
***************************************************************************/
//add by threewater 2003-12-8
static void init_s3c2410_iis_bus_rxtx(void)
{
        IISCON = 0;
        IISMOD = 0;
        IISFIFOC = 0;

     /* 44 KHz , 384fs */
 IISPSR = (IISPSR_A(iispsr_value(S_CLOCK_FREQ, 44100))
  | IISPSR_B(iispsr_value(S_CLOCK_FREQ, 44100)));
 IISCON = (IISCON_TX_DMA  /* Transmit DMA service request */
    |IISCON_RX_DMA  /* Receive Channel idle */
  |IISCON_PRESCALE); /* IIS Prescaler Enable */
  IISMOD = (IISMOD_SEL_MA         /* Master mode */
    | IISMOD_SEL_BOTH         /* Transmit and Receive mode*/
  | IISMOD_CH_RIGHT       /* Low for left channel */
  | IISMOD_FMT_MSB        /* MSB-justified format */
  | IISMOD_BIT_16         /* Serial data bit/channel is 16 bit */
  | IISMOD_FREQ_384       /* Master clock freq = 384 fs */
  | IISMOD_SFREQ_32);     /* 32 fs */
 IISFIFOC = (IISFCON_TX_DMA | IISFCON_RX_DMA      /* Transmit and receive FIFO : DMA */
  | IISFCON_TX_EN);       /* Transmit and receive FIFO enable */
 IISCON |= IISCON_EN;  /* IIS enable(start) */
}
/***************************************************************************
**
**
***************************************************************************/
static int __init audio_init_dma(audio_stream_t * s, char *desc)
{
 if(s->dma_ch == DMA_CH2)
  return s3c2410_request_dma("I2SSDO", s->dma_ch, audio_dmaout_done_callback, NULL);
 else if(s->dma_ch == DMA_CH1)
  return s3c2410_request_dma("I2SSDI", s->dma_ch, NULL ,audio_dmain_done_callback); 
 else
  return 1;
}
/***************************************************************************
**
**
***************************************************************************/
static int audio_clear_dma(audio_stream_t * s)
{
 s3c2410_free_dma(s->dma_ch);
 return 0;
}
/***************************************************************************
**
**
***************************************************************************/
int __init s3c2410_uda1341_init(void)
{
 unsigned long flags;
 local_irq_save(flags);
 /* GPB 4: L3CLOCK, OUTPUT */
 set_gpio_ctrl(GPIO_L3CLOCK);
 /* GPB 3: L3DATA, OUTPUT */
 set_gpio_ctrl(GPIO_L3DATA);
 /* GPB 2: L3MODE, OUTPUT */
 set_gpio_ctrl(GPIO_L3MODE);
 /* GPE 3: I2SSDI */
 set_gpio_ctrl(GPIO_E3 | GPIO_PULLUP_EN | GPIO_MODE_I2SSDI);
 /* GPE 0: I2SLRCK */
 set_gpio_ctrl(GPIO_E0 | GPIO_PULLUP_EN | GPIO_MODE_I2SSDI);
 /* GPE 1: I2SSCLK */
 set_gpio_ctrl(GPIO_E1 | GPIO_PULLUP_EN | GPIO_MODE_I2SSCLK);
 /* GPE 2: CDCLK */
 set_gpio_ctrl(GPIO_E2 | GPIO_PULLUP_EN | GPIO_MODE_CDCLK);
 /* GPE 4: I2SSDO */
 set_gpio_ctrl(GPIO_E4 | GPIO_PULLUP_EN | GPIO_MODE_I2SSDO);
 local_irq_restore(flags);
 init_uda1341();
 output_stream.dma_ch = DMA_CH2;
 if (audio_init_dma(&output_stream, "UDA1341 out")) {
  audio_clear_dma(&output_stream);
  printk( KERN_WARNING AUDIO_NAME_VERBOSE
   ": unable to get DMA channels\n" );
  return -EBUSY;
 }
 input_stream.dma_ch = DMA_CH1;
        if (audio_init_dma(&input_stream, "UDA1341 in")) {
                audio_clear_dma(&input_stream);
                printk( KERN_WARNING AUDIO_NAME_VERBOSE
                        ": unable to get DMA channels\n" );
                return -EBUSY;
        }
 
 audio_dev_dsp = register_sound_dsp(&smdk2410_audio_fops, -1);
 audio_dev_mixer = register_sound_mixer(&smdk2410_mixer_fops, -1);
 printk(AUDIO_NAME_VERBOSE " initialized\n");
 return 0;
}
/***************************************************************************
**
**
***************************************************************************/
void __exit s3c2410_uda1341_exit(void)
{
 unregister_sound_dsp(audio_dev_dsp);
 unregister_sound_mixer(audio_dev_mixer);
 audio_clear_dma(&output_stream);
 audio_clear_dma(&input_stream); /* input */
 printk(AUDIO_NAME_VERBOSE " unloaded\n");
}
module_init(s3c2410_uda1341_init);
module_exit(s3c2410_uda1341_exit);