sinhron_rs.vhd

来自「sinhro for rs(204_188)」· VHDL 代码 · 共 27 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Sinhron_RS is

	 Port 
			( data : in  STD_LOGIC;
           clock : in  STD_LOGIC;
			  reset : in  STD_LOGIC;
			  full : in  STD_LOGIC;			  
			  BYTE_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
			  SEL : out  STD_LOGIC_VECTOR (1 downto 0);
           write_A : out  STD_LOGIC;
			  write_B : out  STD_LOGIC;
			  write_C : out  STD_LOGIC;
			  write_D : out  STD_LOGIC;
			  read_en : out  STD_LOGIC;
			  inform : out  STD_LOGIC;
			  oksin : out  STD_LOGIC);
end Sinhron_RS;

architecture Behavioral of Sinhron_RS is

type my_state is (UNLOCK, -- 疱骅