📄 f12x_init.lst
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}
//-----------------------------------------------------------------------------
// CP220x_RST_Low
//-----------------------------------------------------------------------------
//
// Drives the CP220x's Reset Pin Low.
//
void CP220x_RST_Low(void)
{
char SFRPAGE_SAVE = SFRPAGE;
SFRPAGE = CONFIG_PAGE;
P4 &= ~0x20; // Set P4.5 Low
SFRPAGE = SFRPAGE_SAVE;
}
//-----------------------------------------------------------------------------
// CP220x_RST_High
//-----------------------------------------------------------------------------
//
// Drives the CP220x's Reset Pin High.
//
void CP220x_RST_High(void)
{
char SFRPAGE_SAVE = SFRPAGE;
SFRPAGE = CONFIG_PAGE;
P4 |= 0x20; // Set P4.5 High
SFRPAGE = SFRPAGE_SAVE;
}
//-----------------------------------------------------------------------------
// AB4_RST_State
//-----------------------------------------------------------------------------
//
// Returns the state of the AB4's reset pin.
C51 COMPILER V8.08 F12X_INIT 11/04/2008 15:15:23 PAGE 6
//
unsigned char AB4_RST_State(void)
{
char rst_pin_state;
char SFRPAGE_SAVE = SFRPAGE;
SFRPAGE = CONFIG_PAGE;
rst_pin_state = P4 & 0x20; // Get P4.5 State
SFRPAGE = SFRPAGE_SAVE;
return rst_pin_state;
}
//-----------------------------------------------------------------------------
// Local Initialization Routines
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// PORT_Init
//-----------------------------------------------------------------------------
//
// Configure UART1, Interrupts, Crossbar and GPIO ports
//
void PORT_Init (void)
{
char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
SFRPAGE = CONFIG_PAGE; // set SFR page
P0MDOUT |= 0x01; // set TX1 to push-pull
P1MDOUT |= 0x40; // Set P1.6(TB_LED) to push-pull
P2MDOUT |= 0x0C; // Set P2.2(AB4_LED1) and P2.3(AB4_LED2)
// to push-pull
// all pins used by the external memory interface are in push-pull mode
P4MDOUT = 0xC0;
P5MDOUT = 0xFF;
P6MDOUT = 0xFF;
P7MDOUT = 0xFF;
P4 = 0xDF; // /WR, /RD, are high, RESET is low
P5 = 0xFF;
P6 = 0xFF; // P5, P6 contain the address lines
P7 = 0xFF; // P7 contains the data lines
TCON &= ~0x01; // Make /INT0 level triggered
// Enable UART0, CP0, and /INT0. This puts /INT0 on P0.3.
XBR0 = 0x80;
XBR1 = 0x04;
XBR2 = 0x44;
SFRPAGE = SFRPAGE_SAVE; // Restore SFR page
}
//-----------------------------------------------------------------------------
// SYSCLK_Init
//-----------------------------------------------------------------------------
//
// This routine initializes the system clock.
//
void SYSCLK_Init (void)
{
int i; // software timer
char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
C51 COMPILER V8.08 F12X_INIT 11/04/2008 15:15:23 PAGE 7
SFRPAGE = CONFIG_PAGE; // set SFR page
OSCICN = 0x83; // set internal oscillator to run
// at its maximum frequency
CLKSEL = 0x00; // Select the internal osc. as
// the SYSCLK source
//Turn on the PLL and increase the system clock by a factor of M/N
PLL0CN = 0x00; // Set internal osc. as PLL source
SFRPAGE = LEGACY_PAGE;
FLSCL = 0x30; // Set FLASH read time for 100 MHz clk
SFRPAGE = CONFIG_PAGE;
PLL0CN |= 0x01; // Enable Power to PLL
PLL0DIV = 0x01; // Set Pre-divide value to N (N = 1)
PLL0MUL = 0x04; // Multiply SYSCLK by M (M=4)
PLL0FLT = 0x01; // Set the PLL filter register for
// a reference clock from 12.2 - 19.5 MHz
// and an output clock from 65 - 100 MHz
for (i=0; i < 256; i++) ; // Wait at least 5us
PLL0CN |= 0x02; // Enable the PLL
while(!(PLL0CN & 0x10)); // Wait until PLL frequency is locked
CLKSEL = 0x02; // Select PLL as SYSCLK source
SFRPAGE = SFRPAGE_SAVE; // Restore SFR page
}
//-----------------------------------------------------------------------------
// EMIF_Init
//-----------------------------------------------------------------------------
//
// Configure the External Memory Interface for both on and off-chip access.
//
void EMIF_Init (void)
{
char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
SFRPAGE = LEGACY_PAGE;
EMI0CF = 0xFB; // Split-mode (banked), non-multiplexed
// on P4 - P7
EMI0TC = 0xFF; // This constant may be modified
// according to SYSCLK to meet the
// timing requirements for the CP2200
EMI0CN = 0x20; // Page of XRAM accessed by EMIF
SFRPAGE = SFRPAGE_SAVE; // Restore SFR page
}
//===============
// CONDITIONAL
//===============
#if(UART_ENABLED)
//-----------------------------------------------------------------------------
// UART1_Init
//-----------------------------------------------------------------------------
//
// Configure the UART1 using Timer1, for <baudrate> and 8-N-1.
C51 COMPILER V8.08 F12X_INIT 11/04/2008 15:15:23 PAGE 8
//
void UART1_Init (void)
{
char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
SFRPAGE = UART1_PAGE;
SCON1 = 0x10; // SCON1: mode 0, 8-bit UART, enable RX
SFRPAGE = TIMER01_PAGE;
TMOD &= ~0xF0;
TMOD |= 0x20; // TMOD: timer 1, mode 2, 8-bit reload
if (SYSCLK/BAUDRATE/2/256 < 1) {
TH1 = -(SYSCLK/BAUDRATE/2);
CKCON |= 0x10; // T1M = 1; SCA1:0 = xx
} else if (SYSCLK/BAUDRATE/2/256 < 4) {
TH1 = -(SYSCLK/BAUDRATE/2/4);
CKCON &= ~0x13; // Clear all T1 related bits
CKCON |= 0x01; // T1M = 0; SCA1:0 = 01
} else if (SYSCLK/BAUDRATE/2/256 < 12) {
TH1 = -(SYSCLK/BAUDRATE/2/12);
CKCON &= ~0x13; // T1M = 0; SCA1:0 = 00
} else {
// Adjust for truncation in special case
// Note: Additional cases may be required if the system clock is changed.
#if ((BAUDRATE == 115200) && (SYSCLK == 98000000))
TH1 = -((SYSCLK/BAUDRATE/2/48)+1);
#else
TH1 = -(SYSCLK/BAUDRATE/2/48);
#endif
CKCON &= ~0x13; // Clear all T1 related bits
CKCON |= 0x02; // T1M = 0; SCA1:0 = 10
}
TL1 = TH1; // initialize Timer1
TR1 = 1; // start Timer1
SFRPAGE = UART1_PAGE;
TI1 = 1; // Indicate TX1 ready
SFRPAGE = SFRPAGE_SAVE; // Restore SFR page
}
//-----------------------------------------------------------------------------
// _getkey
//-----------------------------------------------------------------------------
//
// SFR Paged version of _getkey
//
char _getkey () {
char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
char c;
SFRPAGE = UART1_PAGE;
while (!RI1);
c = SBUF1;
RI1 = 0;
SFRPAGE = SFRPAGE_SAVE;
C51 COMPILER V8.08 F12X_INIT 11/04/2008 15:15:23 PAGE 9
return (c);
}
//-----------------------------------------------------------------------------
// putchar
//-----------------------------------------------------------------------------
//
// SFR Paged version of putchar
//
char putchar (char c) {
char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
SFRPAGE = UART1_PAGE;
// output CR
if (c == '\n') {
while (!TI1);
TI1 = 0;
SBUF1 = 0x0d;
}
// output character
while (!TI1);
TI1 = 0;
SBUF1 = c;
SFRPAGE = SFRPAGE_SAVE;
return (c);
}
#endif // UART_ENABLED
#endif // MCU == F120
525
526 //-----------------------------------------------------------------------------
527 // End Of File
528 //-----------------------------------------------------------------------------
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = ---- ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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