24lc64.c

8051单片机访问外围器件的代码

/**
 * @file
 * Driver for the EEPROM Chip 24LC64
 * 
 * 24LC64.c
 * Copyright(C) 2007 Agate Logic Corporation. All rights reserved.
 * This file is licensed under the terms of Agate Logic SDK License Agreement.
 * 
 * @author [e-mail]
*/

#define EP24LC64_GLOBALS	///< define macro "EP24LC64_GLOBALS" as empty
#define EEPROM_USE_IP

#include <AG1F1.h>
#include "24LC64.h"

#ifdef	EEPROM_USE_IP
/**
 * @brief Initial EEPROM 24LC64
 * 
 * The Function set the Clock Prescale and enable the I2C core that communicate with 24LC64
 * 
 * @param prer Prescale of the Clock to communicate with 24LC64
 * 
 * @return N/A
*/
void  EP24LC64_Init (uint prer)
{   
		uchar prerh;
		uchar prerl;
		
		prerl = prer & 0xff;		
		prerh = (prer >> 8) & 0xff;		
		// program internal registers
		I2C_PRERlo_ADDR = prerl;		// load prescaler lo-byte
		I2C_PRERhi_ADDR = prerh;		// load prescaler hi-byte
		I2C_CTR_ADDR = CTR_CORE_EN;		// enable core
}

/**
 * @brief Check status register to see whether 24LC64 is acknowledged to the communication.
 * 
 * Loop check the status register(I2C_SR_ADDR) until bit 1 of it is set
 * which means 24LC64 is acknowledged to the communication, then function return.
 * 
 * @return N/A
*/
void	Check_Status(void)
{
	uchar rddata;
	do
	{
		rddata = I2C_SR_ADDR;	//read Status Register
	}
	while(rddata & 0x2);
}

/**
 * @brief Write an array of datas into the address specified of EEPROM 24LC64.
 * 
 * The Function write the data array specified by dataarr into the address
 * specified by addr of EEPROM 24LC64.
 * The length of the array is specified by data_length and count by byte.
 * 
 * @param addr The target address of EEPROM 24LC64 to write into
 * @param dataarr The source data array to write
 * @param data_length The length of the source data array
 * 
 * @return N/A
*/
void	EP24LC64_write(uint addr, uchar* dataarr, uchar data_length)
{
	uchar addrh;
	uchar addrl;
	if(data_length==0)
		return;
	addrl = addr & 0xff;
	addrh = (addr >> 8) & 0xff;

	// drive slave address
	I2C_TXR_ADDR = 0xA0 ; 		// present slave address, set write-bit
	I2C_CR_ADDR = COM_STA_WR ; 		// set command (start, write)
	Check_Status();

	// send memory address
	I2C_TXR_ADDR = addrh; // present slave's memory high address
	I2C_CR_ADDR = COM_WR; // set command (write)
	Check_Status();
	I2C_TXR_ADDR = addrl; // present slave's memory low address
	I2C_CR_ADDR = COM_WR; // set command (write) 	
	Check_Status();
	for(;data_length>0;data_length--)
	{
		I2C_TXR_ADDR=*dataarr;
		dataarr++;
		if(data_length>1)
			I2C_CR_ADDR=COM_WR;//just write
		else
			I2C_CR_ADDR=COM_STO_WR;//the last one need send stop condition after write
		Check_Status();
	}
}

/**
 * @brief Read an array of datas from the address specified of EEPROM 24LC64.
 * 
 * The Function read the data array specified by dataarr from the address
 * specified by addr of EEPROM 24LC64.
 * The length of the array is specified by data_length and count by byte.
 * 
 * @param addr The source address of EEPROM 24LC64 to read from
 * @param dataarr The target data array to write
 * @param data_length The length of data to read
 * 
 * @return N/A
*/
void	EP24LC64_read(uint addr, uchar* dataarr, uchar data_length)
{
	uchar addrh;
	uchar addrl;
	if(data_length==0)
		return;
	addrl = addr & 0xff;
	addrh = (addr >> 8) & 0xff;

	// drive slave address
	I2C_TXR_ADDR = 0xA0 ; 		// present slave address, set write-bit
	I2C_CR_ADDR = COM_STA_WR ; 		// set command (start, write)
	Check_Status();
	// send memory address
	I2C_TXR_ADDR = addrh; // present slave's memory high address
	I2C_CR_ADDR = COM_WR; // set command (write)
	Check_Status();
	I2C_TXR_ADDR = addrl; // present slave's memory low address
	I2C_CR_ADDR = COM_WR; // set command (write) 	
	Check_Status();

	// drive slave address
	I2C_TXR_ADDR = 0xA1 ;		// present slave address, set read-bit
	I2C_CR_ADDR = COM_STA_WR ;	// set command (start, write)
	Check_Status();

	for(;data_length>0;data_length--)
	{
		if(data_length==1)
			I2C_CR_ADDR = COM_RD_NACK;// set command (read, nack_read)
		else
			I2C_CR_ADDR = COM_RD;// set command (read, ack_read)
		Check_Status();
		
		*dataarr = I2C_RXR_ADDR;
		dataarr++;
	}
	I2C_CR_ADDR = COM_STO_RD;	// set command (stop, read)	 	
}
#else
uchar bdata btdata;
sbit a0=btdata^0;
sbit a1=btdata^1;
sbit a2=btdata^2;
sbit a3=btdata^3;
sbit a4=btdata^4;
sbit a5=btdata^5;
sbit a6=btdata^6;
sbit a7=btdata^7;

void	EP24LC64_delay(uchar times)
{
	while((times--)>0);
}

void	EP24LC64_start_cond(void)
{
	SDADIR=0;
	SCL=0;
	EP24LC64_delay(1);
	SDA=1;
	EP24LC64_delay(1);
	SCL=1;
	EP24LC64_delay(1);
	SDA=0;
	EP24LC64_delay(1);
	SCL=0;
}

void	EP24LC64_stop_cond(void)
{
	SDADIR=0;
	SCL=0;
	EP24LC64_delay(1);
	SDA=0;
	EP24LC64_delay(1);
	SCL=1;
	EP24LC64_delay(1);
	SDA=1;
	EP24LC64_delay(1);
	SCL=0;
}

uchar	EP24LC64_write_byte(uchar wrdata)
{
	uchar ucTmp;
	uchar ucTmp1;
	SDADIR=0;
	btdata=wrdata;
	EP24LC64_delay(1);
	SDA=a7;EP24LC64_delay(1);SCL=1;EP24LC64_delay(2);SCL=0;
	SDA=a6;EP24LC64_delay(1);SCL=1;EP24LC64_delay(2);SCL=0;
	SDA=a5;EP24LC64_delay(1);SCL=1;EP24LC64_delay(2);SCL=0;
	SDA=a4;EP24LC64_delay(1);SCL=1;EP24LC64_delay(2);SCL=0;
	SDA=a3;EP24LC64_delay(1);SCL=1;EP24LC64_delay(2);SCL=0;
	SDA=a2;EP24LC64_delay(1);SCL=1;EP24LC64_delay(2);SCL=0;
	SDA=a1;EP24LC64_delay(1);SCL=1;EP24LC64_delay(2);SCL=0;
	SDA=a0;EP24LC64_delay(1);SCL=1;EP24LC64_delay(2);SCL=0;
	SDADIR=1;
	SCL=1;
	EP24LC64_delay(1);
	ucTmp=1;
	ucTmp1=SDAPORT;
	if((ucTmp1&SDAAND)==0)
		ucTmp=0;
	SCL=0;
	return ucTmp;
}

uchar	EP24LC64_read_byte(uchar generate_acq)
{
	uchar ucTmp1;
	SDADIR=1;
	EP24LC64_delay(1);
	SCL=1;EP24LC64_delay(1);ucTmp1=SDAPORT;a7=((ucTmp1&SDAAND)==SDAAND)?1:0;SCL=0;EP24LC64_delay(1);
	SCL=1;EP24LC64_delay(1);ucTmp1=SDAPORT;a6=((ucTmp1&SDAAND)==SDAAND)?1:0;SCL=0;EP24LC64_delay(1);
	SCL=1;EP24LC64_delay(1);ucTmp1=SDAPORT;a5=((ucTmp1&SDAAND)==SDAAND)?1:0;SCL=0;EP24LC64_delay(1);
	SCL=1;EP24LC64_delay(1);ucTmp1=SDAPORT;a4=((ucTmp1&SDAAND)==SDAAND)?1:0;SCL=0;EP24LC64_delay(1);
	SCL=1;EP24LC64_delay(1);ucTmp1=SDAPORT;a3=((ucTmp1&SDAAND)==SDAAND)?1:0;SCL=0;EP24LC64_delay(1);
	SCL=1;EP24LC64_delay(1);ucTmp1=SDAPORT;a2=((ucTmp1&SDAAND)==SDAAND)?1:0;SCL=0;EP24LC64_delay(1);
	SCL=1;EP24LC64_delay(1);ucTmp1=SDAPORT;a1=((ucTmp1&SDAAND)==SDAAND)?1:0;SCL=0;EP24LC64_delay(1);
	SCL=1;EP24LC64_delay(1);ucTmp1=SDAPORT;a0=((ucTmp1&SDAAND)==SDAAND)?1:0;SCL=0;EP24LC64_delay(1);
	SDADIR=0;
	EP24LC64_delay(1);
	if((generate_acq&0x01)==0x01)
		SDA=0;
	else
		SDA=1;
	EP24LC64_delay(1);
	SCL=1;EP24LC64_delay(2);SCL=0;EP24LC64_delay(1);
	return(btdata);
}

/**
 * @brief Initial EEPROM 24LC64
 * 
 * The Function does nothing just compatable with IP functions
 * 
 * @return N/A
*/
void  EP24LC64_Init (uint prer)
{   
}

void	EP24LC64_write(uint addr, uchar* dataarr, uchar data_length)
{
	uchar ucTmp;
	if(data_length==0)
		return;
start_cond:
	EP24LC64_start_cond();
	while(EP24LC64_write_byte(0xA0))
	{
		EP24LC64_delay(1);
		goto start_cond;
	}
	ucTmp=addr>>8;
	EP24LC64_write_byte(ucTmp);
	ucTmp=addr;
	EP24LC64_write_byte(ucTmp);
	for(;data_length>0;data_length--)
	{
		ucTmp=*dataarr;
		dataarr++;
		EP24LC64_write_byte(ucTmp);
	}
	EP24LC64_stop_cond();
}

void	EP24LC64_read(uint addr, uchar* dataarr, uchar data_length)
{
	uchar ucTmp;
	if(data_length==0)
		return;
start_cond:
	EP24LC64_start_cond();
	while(EP24LC64_write_byte(0xA0))
	{
		EP24LC64_delay(1);
		goto start_cond;
	}
	ucTmp=addr>>8;
	EP24LC64_write_byte(ucTmp);
	ucTmp=addr;
	EP24LC64_write_byte(ucTmp);
	EP24LC64_stop_cond();
	EP24LC64_start_cond();
	EP24LC64_write_byte(0xA1);
	for(;data_length>0;data_length--)
	{
		if(data_length==1)
			ucTmp=EP24LC64_read_byte(0);
		else
			ucTmp=EP24LC64_read_byte(1);
		*dataarr=ucTmp;
		dataarr++;
	}
	EP24LC64_stop_cond();
}
#endif

uchar EP24LC64_readbyte(uint addr)
{
	uchar ucTmp;
	EP24LC64_read(addr, &ucTmp, 1);
	return ucTmp;
}