📄 fmd.cpp
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}
}
WRITE_COMMAND(ulBlockAddress, CLEAR_STATUS_CMD);
WRITE_COMMAND(ulBlockAddress, READ_ARRAY_CMD);
return NumWriteBytes;
}
#endif
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Function: FMD_GetBlockStatus()
Description: Returns the status of a block. For read-only blocks, checks the sector
info data for the first sector of the block. Block is always good, so no need to check.
Returns: Block status.
------------------------------------------------------------------------------*/
DWORD FMD_GetBlockStatus(BLOCK_ID blockID)
{
SECTOR_ADDR Sector = blockID * g_FMDInfo.SectorsPerBlock;
SectorInfo SI;
DWORD dwResult = 0;
#if flash_debug
RETAILMSG(1, (TEXT("FMD_GetBlockStatus: id =%x ).\r\n"), blockID));
#endif
if (!FMD_ReadSector(Sector, NULL, &SI, 1))
return BLOCK_STATUS_UNKNOWN;
if (!(SI.bOEMReserved & OEM_BLOCK_READONLY))
dwResult |= BLOCK_STATUS_READONLY;
if (!(SI.bOEMReserved & OEM_BLOCK_RESERVED))
dwResult |= BLOCK_STATUS_RESERVED;
#if flash_debug
RETAILMSG(1, (TEXT("FMD_GetBlockStatus: over. %x\r\n"),dwResult ));
#endif
return dwResult;
}
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Function: FMD_SetBlockStatus()
Description: Sets the status of a block.
Returns: TRUE if no errors in setting.
------------------------------------------------------------------------------*/
BOOL FMD_SetBlockStatus(BLOCK_ID blockID, DWORD dwStatus)
{
#if flash_debug
RETAILMSG(1, (TEXT("FMD_SetBlockStatus: id =%x status =%x).\r\n"), blockID,dwStatus));
#endif
if (dwStatus & (BLOCK_STATUS_READONLY | BLOCK_STATUS_RESERVED)) {
SECTOR_ADDR Sector = blockID * g_FMDInfo.SectorsPerBlock;
SectorInfo SI;
if (!FMD_ReadSector(Sector, NULL, &SI, 1)) {
return FALSE;
}
if (dwStatus & BLOCK_STATUS_READONLY) {
SI.bOEMReserved &= ~OEM_BLOCK_READONLY;
}
if (dwStatus & BLOCK_STATUS_RESERVED) {
SI.bOEMReserved &= ~OEM_BLOCK_RESERVED;
}
if (!FMD_WriteSector (Sector, NULL, &SI, 1)) {
return FALSE;
}
}
#if flash_debug
RETAILMSG(1, (TEXT("FMD_SetBlockStatus over: id =%x status =%x).\r\n"), blockID,dwStatus));
#endif
return TRUE;
}
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Function: FMD_EraseBlock()
Description: Erases the specified Flash block.
Returns: Boolean indicating success.
------------------------------------------------------------------------------*/
BOOL FMD_EraseBlock(BLOCK_ID blockID)
{
volatile ULONG ulBlockAddress = 0;
ULONG ulStatus = 0;
BOOL bLastMode = SetKMode(TRUE);
int i,j;
ULONG ulCount=0;
volatile PUSHORT pusDest16;
volatile PULONG pusDest32;
DWORD m_offset=0;
#if 1//flash_debug
RETAILMSG(1, (TEXT("FMD_EraseBlock: id =%x ).\r\n"), blockID));
#endif
// Determine the address for the specified block.
ulBlockAddress = g_FMDInfo.BaseAddress + (blockID * g_FMDInfo.BlockSize);
pusDest16= (PUSHORT)ulBlockAddress;
pusDest32= (PULONG)ulBlockAddress;
if(GetEraseFlashSectorIndex(ulBlockAddress-g_FMDInfo.ChipBaseAddress)==FALSE)
{
RETAILMSG(1, (TEXT("ERASE Block error,not aligned\r\n")));
return FALSE;
}
if(g_FlashRegion[g_FMDInfo.gdwCurEraseRegion].block_size==g_FMDInfo.BlockSize)
{
#if 0
if(SetBlockLock(blockID, 1, FALSE)==FALSE)
{
RETAILMSG(1, (TEXT("IntelFlashClearLockBits: id =%x ).\r\n"), blockID));
return FALSE;
}
#endif
SetWriteProtect(FALSE);
#if 0
// Issue erase and confirm command.
// Note: eventually this should be changed to issue mass block erases, then loop to
// verify each completes.
WRITE_COMMAND(ulBlockAddress, BLOCK_ERASE_CMD);
WRITE_COMMAND(ulBlockAddress, BLOCK_PROCEED_CMD);
do
{
WRITE_COMMAND(ulBlockAddress, READ_STATUS_CMD);
}
while (!CHECK_STATUS(ulBlockAddress, STATUS_READY_MASK));
WRITE_COMMAND(ulBlockAddress, CLEAR_STATUS_CMD);
// TODO
// Set the block back to read array mode...
WRITE_COMMAND(ulBlockAddress, READ_ARRAY_CMD);
#endif
#ifdef flash_amd
if (g_bPairedFlash)
{
#if 0//AMD_unlock
pusDest32= (volatile PULONG)g_FMDInfo.ChipBaseAddress;
//RETAILMSG(1, (TEXT(" 0\r\n")));
//WRITE_ULONG (g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1, (AMD_SETUP_CODE1 << 16) | AMD_SETUP_CODE1);
//WRITE_COMMAND(g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1,AMD_SETUP_CODE1);
// *((ULONG *)g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1)=(AMD_SETUP_CODE1 << 16) | AMD_SETUP_CODE1;
*(pusDest32+ AMD_SETUP_ADDR1)=(AMD_SETUP_CODE1 << 16) | AMD_SETUP_CODE1;
//RETAILMSG(1, (TEXT("DoWordWrite: write over 0-1\r\n")));
//WRITE_ULONG (g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR2, (AMD_SETUP_CODE2 << 16) | AMD_SETUP_CODE2);
//WRITE_COMMAND(g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1,AMD_SETUP_CODE2);
*(pusDest32+ AMD_SETUP_ADDR2)=(AMD_SETUP_CODE2 << 16) | AMD_SETUP_CODE2;
//RETAILMSG(1, (TEXT("DoWordWrite: write over 0-2\r\n")));
//WRITE_ULONG (g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1, (AMD_PROGRAM << 16) | AMD_PROGRAM);
//WRITE_COMMAND(g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1,AMD_PROGRAM);
*(pusDest32+ AMD_SETUP_ADDR1)=(0x0020 << 16) | 0x0020;
#endif
m_offset=ulBlockAddress-g_FMDInfo.ChipBaseAddress;
// Issue erase and confirm command.
// Note: eventually this should be changed to issue mass block erases, then loop to
// verify each completes.
pusDest32= (volatile PULONG)g_FMDInfo.ChipBaseAddress;
WRITE_COMMAND(pusDest32+AMD_SETUP_ADDR1, AMD_SETUP_CODE1);
//*(pusDest32+ AMD_SETUP_ADDR1)=(AMD_SETUP_CODE1 << 16) | AMD_SETUP_CODE1;
WRITE_COMMAND(pusDest32+AMD_SETUP_ADDR2, AMD_SETUP_CODE2);
//*(pusDest32+ AMD_SETUP_ADDR2)=(AMD_SETUP_CODE2 << 16) | AMD_SETUP_CODE2;
WRITE_COMMAND(pusDest32+AMD_SETUP_ADDR1, AMD_SETUP_ERASE);
//*(pusDest32+ AMD_SETUP_ADDR1)=(AMD_SETUP_ERASE << 16) | AMD_SETUP_ERASE;
WRITE_COMMAND(pusDest32+AMD_SETUP_ADDR1, AMD_SETUP_CODE1);
//*(pusDest32+ AMD_SETUP_ADDR1)=(AMD_SETUP_CODE1 << 16) | AMD_SETUP_CODE1;
WRITE_COMMAND(pusDest32+AMD_SETUP_ADDR2, AMD_SETUP_CODE2);
//*(pusDest32+ AMD_SETUP_ADDR2)=(AMD_SETUP_CODE2 << 16) | AMD_SETUP_CODE2;
#if flash_debug
RETAILMSG(1, (TEXT("erase: 1\r\n")));
#endif
DelayInuSec(100);
//WRITE_COMMAND(ulBlockAddress, AMD_BLOCK_ERASE);
//pusDest32=(PULONG)ulBlockAddress;
*(pusDest32+(m_offset>>2))= (AMD_BLOCK_ERASE<<16)|AMD_BLOCK_ERASE;
#if flash_debug
RETAILMSG(1, (TEXT("erase: 2\r\n")));
#endif
DelayInuSec(100);
ulCount = 0;
//while (!CHECK_STATUS(ulBlockAddress, AMD_SECTOR_ERASE_TIMER))
while ((*(pusDest32+(m_offset>>2)) &AMD_SECTOR_ERASE_TIMER)!=AMD_SECTOR_ERASE_TIMER)
{
DelayInuSec(1);
if ( ulCount++ == 1000 )
{
RETAILMSG(1, (TEXT("erase: Timed out writing buffered data 1\r\n")));
return 0;
}
}
}
else
{
pusDest16=(PUSHORT)g_FMDInfo.ChipBaseAddress;
// Issue erase and confirm command.
// Note: eventually this should be changed to issue mass block erases, then loop to
// verify each completes.
// WRITE_COMMAND(g_FMDInfo.ChipBaseAddress+AMD_SETUP_ADDR1, AMD_SETUP_CODE1);
*(pusDest16+ AMD_SETUP_ADDR1)= AMD_SETUP_CODE1;
//WRITE_COMMAND(g_FMDInfo.ChipBaseAddress+AMD_SETUP_ADDR2, AMD_SETUP_CODE2);
*(pusDest16+ AMD_SETUP_ADDR2)= AMD_SETUP_CODE2;
//WRITE_COMMAND(g_FMDInfo.ChipBaseAddress+AMD_SETUP_ADDR1, AMD_SETUP_ERASE);
*(pusDest16+ AMD_SETUP_ADDR1)= AMD_SETUP_ERASE;
// WRITE_COMMAND(g_FMDInfo.ChipBaseAddress+AMD_SETUP_ADDR1, AMD_SETUP_CODE1);
*(pusDest16+ AMD_SETUP_ADDR1)= AMD_SETUP_CODE1;
// WRITE_COMMAND(g_FMDInfo.ChipBaseAddress+AMD_SETUP_ADDR2, AMD_SETUP_CODE2);
*(pusDest16+ AMD_SETUP_ADDR2)=AMD_SETUP_CODE2;
#if flash_debug
RETAILMSG(1, (TEXT("16erase: 1\r\n")));
#endif
//DelayInuSec(100);
DelayInuSec(5000);
pusDest16=(PUSHORT)ulBlockAddress;
//WRITE_COMMAND(ulBlockAddress, AMD_BLOCK_ERASE);
*pusDest16 = AMD_BLOCK_ERASE;
#if flash_debug
RETAILMSG(1, (TEXT("16erase: 2\r\n")));
#endif
DelayInuSec(10000);
ulCount = 0;
while (!CHECK_STATUS(ulBlockAddress, AMD_SECTOR_ERASE_TIMER))
{
DelayInuSec(1);
if ( ulCount++ == 10000 )
{
RETAILMSG(1, (TEXT("erase: Timed out writing buffered data 16\r\n")));
return 0;
}
}
}
// TODO
#if flash_debug
RETAILMSG(1, (TEXT("16 erase: 3\r\n")));
#endif
DelayInuSec(100);
// Set the block back to read array mode...
// WRITE_COMMAND((volatile ULONG *)g_FMDInfo.ChipBaseAddress, AMD_RESET);
#endif
SetWriteProtect(TRUE);
#if 1//flash_debug
for(i=0;i<g_FMDInfo.BlockSize/4;i++)
{
if(*((ULONG *)ulBlockAddress+i)!=0xffffffff)
{
RETAILMSG(1, (TEXT("-----EraseBlock error: addr =%x,value=%x ).\r\n"), ulBlockAddress+i, *((ULONG *)ulBlockAddress+i) ));
}
}
#endif
}
else
{
SetWriteProtect(FALSE);
for(j = g_FMDInfo.gdwCurEraseBlock; j< g_FlashRegion[g_FMDInfo.gdwCurEraseRegion].blocks; j++)
{
SetWriteProtect(FALSE);
#ifdef flash_amd
if (g_bPairedFlash)
{
#if 0//AMD_unlock
pusDest32= (volatile PULONG)g_FMDInfo.ChipBaseAddress;
//RETAILMSG(1, (TEXT(" 0\r\n")));
//WRITE_ULONG (g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1, (AMD_SETUP_CODE1 << 16) | AMD_SETUP_CODE1);
//WRITE_COMMAND(g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1,AMD_SETUP_CODE1);
// *((ULONG *)g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1)=(AMD_SETUP_CODE1 << 16) | AMD_SETUP_CODE1;
*(pusDest32+ AMD_SETUP_ADDR1)=(AMD_SETUP_CODE1 << 16) | AMD_SETUP_CODE1;
//RETAILMSG(1, (TEXT("DoWordWrite: write over 0-1\r\n")));
//WRITE_ULONG (g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR2, (AMD_SETUP_CODE2 << 16) | AMD_SETUP_CODE2);
//WRITE_COMMAND(g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1,AMD_SETUP_CODE2);
*(pusDest32+ AMD_SETUP_ADDR2)=(AMD_SETUP_CODE2 << 16) | AMD_SETUP_CODE2;
//RETAILMSG(1, (TEXT("DoWordWrite: write over 0-2\r\n")));
//WRITE_ULONG (g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1, (AMD_PROGRAM << 16) | AMD_PROGRAM);
//WRITE_COMMAND(g_FMDInfo.ChipBaseAddress+ AMD_SETUP_ADDR1,AMD_PROGRAM);
*(pusDest32+ AMD_SETUP_ADDR1)=(0x0020 << 16) | 0x0020;
#endif
m_offset=ulBlockAddress-g_FMDInfo.ChipBaseAddress;
// Issue erase and confirm command.
// Note: eventually this should be changed to issue mass block erases, then loop to
// verify each completes.
pusDest32= (volatile PULONG)g_FMDInfo.ChipBaseAddress;
WRITE_COMMAND(pusDest32+AMD_SETUP_ADDR1, AMD_SETUP_CODE1);
//*(pusDest32+ AMD_SETUP_ADDR1)=(AMD_SETUP_CODE1 << 16) | AMD_SETUP_CODE1;
WRITE_COMMAND(pusDest32+AMD_SETUP_ADDR2, AMD_SETUP_CODE2);
//*(pusDest32+ AMD_SETUP_ADDR2)=(AMD_SETUP_CODE2 << 16) | AMD_SETUP_CODE2;
WRITE_COMMAND(pusDest32+AMD_SETUP_ADDR1, AMD_SETUP_ERASE);
//*(pusDest32+ AMD_SETUP_ADDR1)=(AMD_SETUP_ERASE << 16) | AMD_SETUP_ERASE;
WRITE_COMMAND(pusDest32+AMD_SETUP_ADDR1, AMD_SETUP_CODE1);
//*(pusDest32+ AMD_SETUP_ADDR1)=(AMD_SETUP_CODE1 << 16) | AMD_SETUP_CODE1;
WRITE_COMMAND(pusDest32+AMD_SETUP_ADDR2, AMD_SETUP_CODE2);
//*(pusDest32+ AMD_SETUP_ADDR2)=(AMD_SETUP_CODE2 << 16) | AMD_SETUP_CODE2;
#if flash_debug
RETAILMSG(1, (TEXT("erase: 1\r\n")));
#endif
DelayInuSec(100);
//WRITE_COMMAND(ulBlockAddress, A⌨️ 快捷键说明
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