📄 ep93xx.h
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//****************************************************************************
//
// EP93XX.h - The common definition for ep93xx
//
// Copyright (c) 2006 Cirrus Logic, Inc.
//
//****************************************************************************
#ifndef EP93XX_H
#define EP93XX_H
#ifdef __cplusplus
extern "C" {
#endif
#define REGS_BASE 0x80000000
// DMA
#define DMA_BASE (REGS_BASE + 0x00000000)
#define M2PCH0 (DMA_BASE + 0x0000)
#define M2PCH1 (DMA_BASE + 0x0040)
#define M2PCH2 (DMA_BASE + 0x0080)
#define M2PCH3 (DMA_BASE + 0x00C0)
#define M2MCH0 (DMA_BASE + 0x0100)
#define M2MCH1 (DMA_BASE + 0x0140)
#define M2PCH5 (DMA_BASE + 0x0200)
#define M2PCH4 (DMA_BASE + 0x0240)
#define M2PCH7 (DMA_BASE + 0x0280)
#define M2PCH6 (DMA_BASE + 0x02C0)
#define M2PCH9 (DMA_BASE + 0x0300)
#define M2PCH8 (DMA_BASE + 0x0340)
#define DMACHARB (DMA_BASE + 0x0380)
#define DMAGLINT (DMA_BASE + 0x03C0)
// Ethernet MAC
#define ETHERNET_BASE (REGS_BASE + 0x00010000)
#define RXCTL 0x0000 /* Receive Control */
#define TXCTL 0x0004 /* Transmit Control */
#define TESTCTL 0x0008 /* Test Control */
#define MIICMD 0x0010 /* MII(Media Independent Intf) Command */
#define MIIDATA 0x0014 /* MII Data */
#define MIISTS 0x0018 /* MII Status */
#define SELFCTL 0x0020 /* Self Control for LED interface */
#define INTEN 0x0024 /* Interrupt Enable */
#define INTSTSP 0x0028 /* Interrupt Status Preserve */
#define INTSTSC 0x002C /* Interrupt Status Clear */
#define GT 0x0040 /* General Timer */
#define FCT 0x0044 /* Flow Control Timer */
#define FCF 0x0048 /* Flow Control Format */
#define AFP 0x004C /* Address Filter Pointer */
#define HASHTBL 0x0050 /* Logical Address Filter (Hash Table) */
#define INDAD 0x0050 /* Individual Address, IA */
#define GLINTSTS 0x0060 /* Cardbus Function Event Mask Register */
#define GLINTMSK 0x0064 /* Cardbus Function Event Mask Register */
#define GLINTROSSTS 0x0068 /* Cardbus Function Event Mask Register */
#define GLINTFRC 0x006C /* Cardbus Function Event Mask Register */
#define TXCOLLCNT 0x0070 /* Transmit Collision Count */
#define RXMISSCNT 0x0074 /* Receive Miss Count */
#define RXRUNTCNT 0x0078 /* Receive Runt Count */
#define BMCTL 0x0080 /* Bus Master Control */
#define BMSTS 0x0084 /* Bus Master Status */
#define RXBCA 0x0088 /* Receive buffer current address, a.k.a. RBCA */
#define RXDQBADD 0x0090 /* Receive Descriptor Queue Base Address */
#define RXDQBLEN 0x0094 /* Receive Descriptor Queue Base Length */
#define RXDQCURLEN 0x0096 /* Receive Descriptor Queue Current Length */
#define RXDCURADD 0x0098 /* Receive Descriptor Current Address */
#define RXDENQ 0x009C /* Receive Descriptor Enqueue */
#define RXSTSQBADD 0x00A0 /* Receive Status Queue Base Address */
#define RXSTSQBLEN 0x00A4 /* Receive Status Queue Base Length */
#define RXSTSQCURLEN 0x00A6 /* Receive Status Queue Current Length */
#define RXSTSQCURADD 0x00A8 /* Receive Status Current Address */
#define RXSTSENQ 0x00AC /* Receive Status Enqueue */
#define TXDQBADD 0x00B0 /* Transmit Descriptor Queue Base Address */
#define TXDQBLEN 0x00B4 /* Transmit Descriptor Queue Base Length */
#define TXDQCURLEN 0x00B6 /* Transmit Descriptor Queue Current Length */
#define TXDQCURADD 0x00B8 /* Transmit Descriptor Current Address */
#define TXDENQ 0x00BC /* Transmit Descriptor Enqueue */
#define TXSTSQBADD 0x00C0 /* Transmit status Queue Base Address */
#define TXSTSQBLEN 0x00C4 /* Transmit Status Queue Base Length */
#define TXSTSQCURLEN 0x00C6 /* Transmit Status Queue Current Length */
#define TXSTSQCURADD 0x00C8 /* Transmit Status Current Address */
#define RXBTH 0x00D0 /* Receive Buffer Threshold */
#define TXBTH 0x00D4 /* Transmit Buffer Threshold */
#define RXSTH 0x00D8 /* Receive Status Threshold */
#define TXSTH 0x00DC /* Transmit Status Threshold */
#define RXDTH 0x00E0 /* Receive Descriptor Threshold */
#define TXDTH 0x00E4 /* Transmit Descriptor Threshold */
#define MAXFRMLEN 0x00E8 /* Maximum Frame Length */
#define RXHLEN 0x00EC /* Receive Header Length */
#define MACCFG0 0x0100 /* MAC Configuration Register 0 */
#define MACCFG1 0x0104 /* MAC Configuration Register 1 */
#define MACCFG2 0x0108 /* MAC Configuration Register 2 */
#define MACCFG3 0x010C /* MAC Configuration Register 3 */
// RXCTL registers bits
#define RXCTL_PAUSEA (1L<<0x14)
#define RXCTL_RxFCE1 (1L<<0x13)
#define RXCTL_RxFCE0 (1L<<0x12)
#define RXCTL_BCRC (1L<<0x11)
#define RXCTL_SRXON (1L<<0x10)
#define RXCTL_RCRCA (1L<<0x0D)
#define RxCTL_RuntA (1L<<0x0C)
#define RXCTL_PA (1L<<0x0B)
#define RXCTL_BA (1L<<0x0A)
#define RXCTL_MA (1L<<0x09)
#define RxCTL_IAHA (1L<<0x08)
#define RXCTL_IA3 (1L<<0x03)
#define RXCTL_IA2 (1L<<0x02)
#define RXCTL_IA1 (1L<<0x01)
#define RXCTL_IA0 (1L<<0x00)
// TXCTL registers bits
#define TXCTL_DEFDIS (1<<0x07)
#define TXCTL_MBE (1<<0x06)
#define TXCTL_ICRC (1<<0x05)
#define TXCTL_TXPD (1<<0x04)
#define TXCTL_OCOLL (1<<0x03)
#define TXCTL_SP (1<<0x02)
#define TXCTL_PB (1<<0x01)
#define TXCTL_STXON (1<<0x00)
// TESTCTL registers bits
#define TESTCTL_MACF (1<<0x07)
#define TESTCTL_MFDX (1<<0x06)
#define TESTCTL_DB (1<<0x05)
// MIICMD registers bits
#define MIICMD_REGAD (0x001F)
#define MIICMD_PHYAD (0x03E0)
#define MIICMD_OP (0xC000)
#define MIICMD_OPREAD (0x8000)
#define MIICMD_OPWRITE (0x4000)
// MIISTS registers bits
#define MIISTS_BUSY (1<<0x00)
// SELFCTL registers bits
#define SELFCTL_MDCDIVMSK (0x7E00)
#define SELFCTL_MDCDIVSHT 9
#define SELFCTL_PSPRS (1<<0x08)
#define SELFCTL_RWP (1<<0x07)
#define SELFCTL_GPO0 (1<<0x05)
#define SELFCTL_PUWE (1<<0x04)
#define SELFCTL_PDWE (1<<0x03)
#define SELFCTL_MIIL (1<<0x02)
#define SELFCTL_RESET (1<<0x00)
// INTEN register bits
#define INTEN_MIE (1L<<0x1d)
#define INTEN_RXBIE (1L<<0x1c)
#define INTEN_RXSQIE (1L<<0x1b)
#define INTEN_TXLEIE (1L<<0x1a)
#define INTEN_ECIE (1L<<0x19)
#define INTEN_TXUHIE (1L<<0x18)
#define INTEN_MOIE (1L<<0x12)
#define INTEN_TXCOIE (1L<<0x11)
#define INTEN_RXROIE (1L<<0x10)
#define INTEN_MIIE (1L<<0x0c)
#define INTEN_PHYSIE (1L<<0x0b)
#define INTEN_TIE (1L<<0x0a)
#define INTEN_SWIE (1L<<0x08)
#define INTEN_TSQIE (1L<<0x03)
#define INTEN_REOFIE (1L<<0x02)
#define INTEN_REOBIE (1L<<0x01)
#define INTEN_RHDRIE (1L<<0x00)
// INTSTSP/INTSTSC register bits
#define INTSTS_RWI (1L<<0x1e)
#define INTSTS_RXMI (1L<<0x1d)
#define INTSTS_RXBI (1L<<0x1c)
#define INTSTS_RXSQI (1L<<0x1b)
#define INTSTS_TXLEI (1L<<0x1a)
#define INTSTS_ECI (1L<<0x19)
#define INTSTS_TXUHI (1L<<0x18)
#define INTSTS_MOI (1L<<0x12)
#define INTSTS_TXCOI (1L<<0x11)
#define INTSTS_RXROI (1L<<0x10)
#define INTSTS_MII (1L<<0x0c)
#define INTSTS_PHYSI (1L<<0x0b)
#define INTSTS_TI (1L<<0x0a)
#define INTSTS_AHBE (1L<<0x09)
#define INTSTS_SWI (1L<<0x08)
#define INTSTS_Other (1L<<0x04)
#define INTSTS_TXSQ (1L<<0x03)
#define INTSTS_RXSQ (1L<<0x02)
// GT register bits
#define GT_GTC (0xFFFF0000)
#define GT_GTP (0x0000FFFF)
// FCT register bits
#define FCT_VALUE (0x00FFFFFF)
// FCF register bits
#define FCF_MACCT (0xFFFF0000)
#define FCF_TPT (0x0000FFFF)
// AFP register bits
#define AFP_MASK (0x07)
#define AFP_IAPRIMARY (0x00)
#define AFP_IASECONDARY1 (0x01)
#define AFP_IASECONDARY2 (0x02)
#define AFP_IASECONDARY3 (0x03)
#define AFP_TX (0x06)
#define AFP_HASH (0x07)
// GLINTMSK register bits
#define GLINTMSK_INT (1L<<0x0F)
// BMCTL register bits
#define BMCTL_MT (1<<0x0d)
#define BMCTL_TT (1<<0x0c)
#define BMCTL_UNH (1<<0x0b)
#define BMCTL_TXCHR (1<<0x0a)
#define BMCTL_TXDIS (1<<0x09)
#define BMCTL_TXEN (1<<0x08)
#define BMCTL_EH2 (1<<0x06)
#define BMCTL_EH1 (1<<0x05)
#define BMCTL_EEOB (1<<0x04)
#define BMCTL_RXCHR (1<<0x02)
#define BMCTL_RXDIS (1<<0x01)
#define BMCTL_RXEN (1<<0x00)
// BMSTS register bits
#define BMSTS_TXACT (1<<0x07)
#define BMSTS_TP (1<<0x04)
#define BMSTS_RXACT (1<<0x03)
#define BMSTS_QID_MASK (0x07)
#define BMSTS_QID_RXDATA (0x00)
#define BMSTS_QID_TXDATA (0x01)
#define BMSTS_QID_RXSTS (0x02)
#define BMSTS_QID_TXSTS (0x03)
#define BMSTS_QID_RXDESC (0x04)
#define BMSTS_QID_TXDESC (0x05)
// RXSTS_T.STS bit
#define RXSTS_RFP (1UL<<0x1f) /* rx frame process bit */
#define RXSTS_RWE (1UL<<0x1e) /* rx without error */
#define RXSTS_EOF (1UL<<0x1d) /* end of frame data */
#define RXSTS_EOB (1UL<<0x1c) /* end of buffer */
#define RXSTS_AM (0x000C0000) /* address match */
#define RXSTS_AM_IA (0x00000000) /* individual address match */
#define RXSTS_AM_GA (0x00040000) /* global address match */
#define RXSTS_AM_HashIA (0x00080000) /* hashed individual address match */
#define RXSTS_AM_HashMC (0x000C0000) /* hashed multicast address match */
#define RXSTS_ERR_MSK (0x003F0000) /* receive error mask */
#define RXSTS_RX_ERR (1UL<<0x15) /* RX_ERR (MII pin) set */
#define RXSTS_OE (1UL<<0x14) /* overrun */
#define RXSTS_FE (1UL<<0x13) /* bad crc or incorrect # of bytes */
#define RXSTS_RUNT (1UL<<0x12) /* frame shorter than 64 bytes */
#define RXSTS_EDATA (1UL<<0x11) /* frame >= MaxFrameLen reg */
#define RXSTS_CRCE (1UL<<0x10) /* bad crc */
#define RXSTS_CRCI (1UL<<0x0F) /* crc included with frame data */
#define RXSTS_HTI_MSK (0x00003F00) /* hash table index */
#define RXSTS_HTI_IA0 (0x00000100) /* frame matched ind addr 0 */
#define RXSTS_HTI_IA1 (0x00000200) /* frame matched ind addr 1 */
#define RXSTS_HTI_IA2 (0x00000400) /* frame matched ind addr 2 */
#define RXSTS_HTI_IA3 (0x00000800) /* frame matched ind addr 3 */
// TXDESC_T bits
#define TXDESC_BL_MSK 0x0fff
#define TXDESC_AF 0x8000 /* used to invalidate frame */
#define TXDESC_BI_MSK 0x7FFF
#define TXDESC_EOF 0x8000 /* end of frame flag */
// TXSTS_T.STS bits
#define TXSTS_BI_MSK 0x7FFF
#define TXSTS_TxFP (1<<0x0f) /* tx frame process bit (chip sets to 1) */
#define TXSTS_TxWE (1<<0x0e) /* tx without error */
#define TXSTS_FA (1<<0x0d) /* frame canceled by host (see TxDesc) */
#define TXSTS_LCRS (1<<0x0c) /* MII CRS sig not asserted */
#define TXSTS_OW (1<<0x0a) /* collision after 60 bytes transmitted*/
#define TXSTS_TxU (1<<0x09) /* bus latency error */
#define TXSTS_EColl (1<<0x08) /* excessive collisions */
#define TXSTS_NColl_MSK (0x001F) /* number of collisions */
#define TXSTS_ERR_MSK (0x3F00) /* error bit mask */
// USB
#define USB_BASE (REGS_BASE + 0x00020000)
#define HCREVISION (USB_BASE + 0x0000)
#define HCCONTROL (USB_BASE + 0x0004)
#define HCCOMMANDSTATUS (USB_BASE + 0x0008)
#define HCINTERRUPTSTATUS (USB_BASE + 0x000C)
#define HCINTERRUPTENABLE (USB_BASE + 0x0010)
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