📄 boot.s
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// Return to the caller.
//
ldmfd r13!, {r4, pc}
//****************************************************************************
//
// CopySdram copys the data receive via the serial port into the on-board
// SDRAM.
//
//****************************************************************************
CopySdram _LABEL_
//
// Save the link register to the stack.
//
stmfd r13!, {r4-r7, lr}
//
// Send the command recieve data from the host.
//
mov r0, _CONST_ 0x3c // '<'
bl SendChar
//
// Read the 4bytes of data, Get the file size.
//
bl ReadLong
mov r6, r0
mov r0, _CONST_ 0x44 // 'D'
bl SendChar
mov r5, r11
//mov r6, _CONST_ 0x40000
copy_loop _LABEL_
//
// Read the 4bytes of data.
//
bl ReadLong
//
// Copy 4bytes word to SDRAM.
//
str r0, [r5], _CONST_ 4
//
// Decrement the count of bytes.
//
subs r6, r6, _CONST_ 4
bne copy_loop
//
// Send the command terminate transfer.
//
mov r0, _CONST_ 0x3e // '<'
bl SendChar
ldmfd r13!, {r4-r7, pc}
//****************************************************************************
//
// The boot code entry.
//
//****************************************************************************
SetUp _LABEL_
//
// Detect the nSDCS3 sync boot base address.
//
ldr r11, =0x00000000
//
// Try a 32-bit wide configuration of SDRAM.
//
ldr r0, =0x00210028
ldr r1, =0x00400000
orr r2, r11, _CONST_ 0x00008800
ldr r3, =0x80060000
str r0, [r3, _CONST_ 0x001c]
bl SdramConfig
//
// Test the SDRAM.
//
mov r0, r11
bl SdramDetect
cmp r0, _CONST_ 0x00000000
beq SdramOk
//
// Try a 16-bit wide configuration of SDRAM.
//
ldr r0, =0x0021002c
ldr r1, =0x00200000
orr r2, r11, _CONST_ 0x00004600
ldr r3, =0x80060000
str r0, [r3, _CONST_ 0x001c]
bl SdramConfig
//
// Test the SDRAM.
//
mov r0, r11
bl SdramDetect
cmp r0, _CONST_ 0x00000000
beq SdramOk
//
// Detect the nSDCS0 base address.
//
ldr r11, =0xc0000000
//
// Try a 32-bit wide configuration of SDRAM.
//
ldr r0, =0x00210028
ldr r1, =0x00400000
orr r2, r11, _CONST_ 0x00008800
ldr r3, =0x80060000
str r0, [r3, _CONST_ 0x0010]
bl SdramConfig
//
// Test the SDRAM.
//
mov r0, r11
bl SdramDetect
cmp r0, _CONST_ 0x00000000
beq SdramOk
//
// Try a 16-bit wide configuration of SDRAM.
//
ldr r0, =0x0021002c
ldr r1, =0x00200000
orr r2, r11, _CONST_ 0x00004600
ldr r3, =0x80060000
str r0, [r3, _CONST_ 0x0010]
bl SdramConfig
//
// Test the SDRAM.
//
mov r0, r11
bl SdramDetect
cmp r0, _CONST_ 0x00000000
beq SdramOk
//
// Detect the nSDCS1 base address.
//
ldr r11, =0xd0000000
//
// Try a 32-bit wide configuration of SDRAM.
//
ldr r0, =0x00210028
ldr r1, =0x00400000
orr r2, r11, _CONST_ 0x00008800
ldr r3, =0x80060000
str r0, [r3, _CONST_ 0x0014]
bl SdramConfig
//
// Test the SDRAM.
//
mov r0, r11
bl SdramDetect
cmp r0, _CONST_ 0x00000000
beq SdramOk
//
// Try a 16-bit wide configuration of SDRAM.
//
ldr r0, =0x0021002c
ldr r1, =0x00200000
orr r2, r11, _CONST_ 0x00004600
ldr r3, =0x80060000
str r0, [r3, _CONST_ 0x0014]
bl SdramConfig
//
// Test the SDRAM.
//
mov r0, r11
bl SdramDetect
cmp r0, _CONST_ 0x00000000
beq SdramOk
//
// Detect the nSDCS2 base address.
//
ldr r11, =0xe0000000
//
// Try a 32-bit wide configuration of SDRAM.
//
ldr r0, =0x00210028
ldr r1, =0x00400000
orr r2, r11, _CONST_ 0x00008800
ldr r3, =0x80060000
str r0, [r3, _CONST_ 0x0018]
bl SdramConfig
//
// Test the SDRAM.
//
mov r0, r11
bl SdramDetect
cmp r0, _CONST_ 0x00000000
beq SdramOk
//
// Try a 16-bit wide configuration of SDRAM.
//
ldr r0, =0x0021002c
ldr r1, =0x00200000
orr r2, r11, _CONST_ 0x00004600
ldr r3, =0x80060000
str r0, [r3, _CONST_ 0x0018]
bl SdramConfig
//
// Test the SDRAM.
//
mov r0, r11
bl SdramDetect
cmp r0, _CONST_ 0x00000000
beq SdramOk
//
// Detect the nSDCS3 async boot base address.
//
ldr r11, =0xf0000000
//
// Try a 32-bit wide configuration of SDRAM.
//
ldr r0, =0x00210028
ldr r1, =0x00400000
orr r2, r11, _CONST_ 0x00008800
ldr r3, =0x80060000
str r0, [r3, _CONST_ 0x001c]
bl SdramConfig
//
// Test the SDRAM.
//
mov r0, r11
bl SdramDetect
cmp r0, _CONST_ 0x00000000
beq SdramOk
//
// Try a 16-bit wide configuration of SDRAM.
//
ldr r0, =0x0021002c
ldr r1, =0x00200000
orr r2, r11, _CONST_ 0x00004600
ldr r3, =0x80060000
str r0, [r3, _CONST_ 0x001c]
bl SdramConfig
//
// Test the SDRAM.
//
mov r0, r11
bl SdramDetect
cmp r0, _CONST_ 0x00000000
beq SdramOk
//
// Send a 'X' to the host to indicate that we did not find SDRAM.
//
mov r0, _CONST_ 0x58 // 'X'
bl SendChar
//
// Loop forever.
//
b .
//
// Save the SDRAM base address to 0x80014780
//
SdramOk _LABEL_
ldr r1, =0x80014780
str r11, [r1]
//
// Loop forever reading commands from the host and performing them.
//
loop _LABEL_
//
// Write the command prompt to the host.
//
mov r0, _CONST_ 0x3f // '?'
bl SendChar
//
// Read a command from the host.
//
bl ReceiveChar
//
// Determine how to handle this command. Is this a 'B'?
//
cmp r0, _CONST_ 0x42 // 'B'
bne loop1
//
// Change the baud rate of the serial port.
//
bl SetBaud
b loop
//
// Is this a 'C'?
//
loop1 _LABEL_
cmp r0, _CONST_ 0x43 // 'C'
bne loop
//
// Copy data into the on-board SDRAM.
//
bl CopySdram
//
// Switch to SDRAM to run second boot.
//
ldr r1, =0x80014780
ldr r11, [r1]
mov pc, r11
nop
b loop
//****************************************************************************
//
// The zero-initialized read-write data used by the application.
//
//****************************************************************************
_BSS_
//****************************************************************************
//
// A buffer to contain 1K bytes of data read from the serial port that is to be
// programmed into the FLASH.
//
//****************************************************************************
_SPACE_ 0x400
Stack _LABEL_
_END_
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