ifspec.ifs

xspice所支持的更为详细和全面的仿真电路示例程序

/* $Id: ifspec.tpl,v 1.1 91/03/18 19:01:11 bill Exp $ */

NAME_TABLE:

Spice_Model_Name:      real_delay
C_Function_Name:       ucm_real_delay
Description:           "A Z ** -1 block working on real data"


PORT_TABLE:

Port_Name:             in               clk             out
Description:           "input"          "clock"         "output"
Direction:             in               in              out
Default_Type:          real             d               real
Allowed_Types:         [real]           [d]             [real]
Vector:                no               no              no
Vector_Bounds:         -                -               -
Null_Allowed:          no               no              no


PARAMETER_TABLE:

Parameter_Name:        delay
Description:           "delay from clk to out"
Data_Type:             real
Default_Value:         1e-9
Limits:                [1e-15 -]
Vector:                no
Vector_Bounds:         -
Null_Allowed:          yes