es1371.c

Minix比较全的源码

int drv_get_irq(char *irq) {
	*irq = dev.irq;
	return OK;
}


int drv_get_frag_size(u32_t *frag_size, int sub_dev) {
	*frag_size = aud_conf[sub_dev].fragment_size;
	return OK;  
}


int drv_set_dma(u32_t dma, u32_t length, int chan) {
	/* dma length in bytes, 
	   max is 64k long words for es1371 = 256k bytes */
	u32_t page, frame_count_reg, dma_add_reg;

	switch(chan) {
		case ADC1_CHAN: page = ADC_MEM_PAGE;
						frame_count_reg = ADC_BUFFER_SIZE;
						dma_add_reg = ADC_PCI_ADDRESS;
						break;
		case DAC1_CHAN: page = DAC_MEM_PAGE;
						frame_count_reg = DAC1_BUFFER_SIZE;
						dma_add_reg = DAC1_PCI_ADDRESS;
						break;;
		case DAC2_CHAN: page = DAC_MEM_PAGE;
						frame_count_reg = DAC2_BUFFER_SIZE;
						dma_add_reg = DAC2_PCI_ADDRESS;
						break;;    
		default: return EIO;
	}
	pci_outb(reg(MEM_PAGE), page);
	pci_outl(reg(dma_add_reg), dma);

	/* device expects long word count in stead of bytes */
	length /= 4;

	/* It seems that register _CURRENT_COUNT is overwritten, but this is
	 * the way to go. The register frame_count_reg is only longword
	 * addressable.
	 * It expects length -1
	 */
	pci_outl(reg(frame_count_reg), (u32_t) (length - 1));

	return OK;
}


/* return status of the interrupt summary bit */
int drv_int_sum(void) {
	return pci_inl(reg(INTERRUPT_STATUS)) & INTR;
}


int drv_int(int sub_dev) {
	u32_t int_status;
	u32_t bit;
	u32_t debug;

	/* return status of interrupt bit of specified channel*/
	switch (sub_dev) {
		case DAC1_CHAN:  bit = DAC1;break;
		case DAC2_CHAN:  bit = DAC2;break;
		case ADC1_CHAN:  bit = ADC;break;
	}

	int_status = pci_inl(reg(INTERRUPT_STATUS)) & bit;

	return int_status;
}


int drv_reenable_int(int chan) {
	u16_t ser_interface, int_en_bit;

	switch(chan) {
		case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
		case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
		case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;    
		default: EINVAL;
	}

	/* clear and reenable an interrupt */
	ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
	pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface & ~int_en_bit);
	pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface | int_en_bit);

	return OK;
}


int drv_pause(int sub_dev) { 
	u32_t pause_bit;

	disable_int(sub_dev); /* don't send interrupts */

	switch(sub_dev) {
		case DAC1_CHAN: pause_bit = P1_PAUSE;break;
		case DAC2_CHAN: pause_bit = P2_PAUSE;break;    
		default: return EINVAL;
	}

	/* pause */
	pci_outl(reg(SERIAL_INTERFACE_CTRL),
			pci_inl(reg(SERIAL_INTERFACE_CTRL)) | pause_bit);

	return OK;
}


int drv_resume(int sub_dev) {
	u32_t pause_bit = 0;

	drv_reenable_int(sub_dev); /* enable interrupts */

	switch(sub_dev) {
		case DAC1_CHAN: pause_bit = P1_PAUSE;break;
		case DAC2_CHAN: pause_bit = P2_PAUSE;break;    
		default: return EINVAL;
	}

	/* clear pause bit */
	pci_outl(reg(SERIAL_INTERFACE_CTRL),
			pci_inl(reg(SERIAL_INTERFACE_CTRL)) & ~pause_bit);

	return OK;
}


PRIVATE int set_bits(u32_t nr_of_bits, int sub_dev) {
	/* set format bits for specified channel. */
	u16_t size_16_bit, ser_interface;

	switch(sub_dev) {
		case ADC1_CHAN: size_16_bit = R1_S_EB; break;
		case DAC1_CHAN: size_16_bit = P1_S_EB; break;
		case DAC2_CHAN: size_16_bit = P2_S_EB; break;    
		default: return EINVAL;
	}

	ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
	ser_interface &= ~size_16_bit;
	switch(nr_of_bits) {
		case 16: ser_interface |= size_16_bit;break;
		case  8: break;
		default: return EINVAL;
	}
	pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface);
	aud_conf[sub_dev].nr_of_bits = nr_of_bits;
	return OK;
}


PRIVATE int set_stereo(u32_t stereo, int sub_dev) {
	/* set format bits for specified channel. */
	u16_t stereo_bit, ser_interface;

	switch(sub_dev) {
		case ADC1_CHAN: stereo_bit = R1_S_MB; break;
		case DAC1_CHAN: stereo_bit = P1_S_MB; break;
		case DAC2_CHAN: stereo_bit = P2_S_MB; break;    
		default: return EINVAL;
	}
	ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
	ser_interface &= ~stereo_bit;
	if (stereo) {
		ser_interface |= stereo_bit;
	} 
	pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface);
	aud_conf[sub_dev].stereo = stereo;

	return OK;
}


PRIVATE int set_sign(u32_t val, int sub_dev) {
	return OK;
}


PRIVATE int set_frag_size(u32_t fragment_size, int sub_dev_nr) {
	if (fragment_size > (sub_dev[sub_dev_nr].DmaSize / 
				sub_dev[sub_dev_nr].NrOfDmaFragments) || 
			fragment_size < sub_dev[sub_dev_nr].MinFragmentSize) {
		return EINVAL;
	}
	aud_conf[sub_dev_nr].fragment_size = fragment_size;

	return OK;
}


PRIVATE int set_sample_rate(u32_t rate, int sub_dev) {
	u32_t src_base_reg;

	if (rate > MAX_RATE || rate < MIN_RATE) {
		return EINVAL;
	}
	/* set the sample rate for the specified channel*/
	switch(sub_dev) {
		case ADC1_CHAN: src_base_reg = SRC_ADC_BASE;break;
		case DAC1_CHAN: src_base_reg = SRC_SYNTH_BASE;break;
		case DAC2_CHAN: src_base_reg = SRC_DAC_BASE;break;    
		default: return EINVAL;
	}
	src_set_rate(&dev, src_base_reg, rate);
	aud_conf[sub_dev].sample_rate = rate;
	return OK;
}


PRIVATE int set_int_cnt(int chan) {
	/* Write interrupt count for specified channel. 
	   After <DspFragmentSize> bytes, an interrupt will be generated  */

	int sample_count; 
	u16_t int_cnt_reg;

	if (aud_conf[chan].fragment_size > 
			(sub_dev[chan].DmaSize / sub_dev[chan].NrOfDmaFragments) 
			|| aud_conf[chan].fragment_size < sub_dev[chan].MinFragmentSize) {
		return EINVAL;
	}

	switch(chan) {
		case ADC1_CHAN: int_cnt_reg = ADC_SAMP_CT; break;
		case DAC1_CHAN: int_cnt_reg = DAC1_SAMP_CT; break;
		case DAC2_CHAN: int_cnt_reg = DAC2_SAMP_CT; break;    
		default: return EINVAL;
	}

	sample_count = aud_conf[chan].fragment_size;

	/* adjust sample count according to sample format */
	if( aud_conf[chan].stereo == TRUE ) sample_count >>= 1;
	switch(aud_conf[chan].nr_of_bits) {
		case 16:   sample_count >>= 1;break;
		case  8:   break;
		default: return EINVAL;
	}    

	/* set the sample count - 1 for the specified channel. */
	pci_outw(reg(int_cnt_reg), sample_count - 1);

	return OK;
}


PRIVATE int get_max_frag_size(u32_t * val, int * len, int sub_dev_nr) {
	*len = sizeof(*val);
	*val = (sub_dev[sub_dev_nr].DmaSize / 
			sub_dev[sub_dev_nr].NrOfDmaFragments);
	return OK;
}


PRIVATE int disable_int(int chan) {
	u16_t ser_interface, int_en_bit;

	switch(chan) {
		case ADC1_CHAN: int_en_bit = R1_INT_EN; break;
		case DAC1_CHAN: int_en_bit = P1_INTR_EN; break;
		case DAC2_CHAN: int_en_bit = P2_INTR_EN; break;    
		default: EINVAL;
	}
	/* clear the interrupt */
	ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL));
	pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface & ~int_en_bit);
}


PRIVATE int get_samples_in_buf (u32_t *samples_in_buf, int *len, int chan) {
	u16_t samp_ct_reg; 
	u16_t curr_samp_ct_reg;
	u16_t samp_ct;  /* nr of samples - 1 that will be played back */
	u16_t curr_samp_ct; /* counts back from SAMP_CT till 0 */

	*len = sizeof(*samples_in_buf);

	switch(chan) {
		case ADC1_CHAN: 
			curr_samp_ct_reg = ADC_CURR_SAMP_CT;
			samp_ct_reg = ADC_SAMP_CT; break;
		case DAC1_CHAN: 
			curr_samp_ct_reg = DAC1_CURR_SAMP_CT;
			samp_ct_reg = DAC1_SAMP_CT; break;
		case DAC2_CHAN: 
			curr_samp_ct_reg = DAC2_CURR_SAMP_CT;
			samp_ct_reg = DAC2_SAMP_CT; break;    
		default: return EINVAL;
	}

	samp_ct = pci_inw(reg(samp_ct_reg));
	curr_samp_ct = pci_inw(reg(curr_samp_ct_reg));

	*samples_in_buf = (u32_t) (sub_dev[chan].BufLength * 8192) + 
		curr_samp_ct;

	return OK;
}


/* returns 1 if there are free buffers */
PRIVATE int free_buf (u32_t *val, int *len, int sub_dev_nr) {
	*len = sizeof(*val);
	if (sub_dev[sub_dev_nr].BufLength ==
			sub_dev[sub_dev_nr].NrOfExtraBuffers) {
		*val = 0;
	}
	else {
		*val = 1;
	}
	return OK;
}


PRIVATE int get_set_volume(struct volume_level *level, int *len, int sub_dev, 
		int flag) {
	*len = sizeof(struct volume_level);
	if (sub_dev == MIXER) {
		return AC97_get_set_volume(level, flag);
	}
	else {
		return EINVAL;
	}
}