📄 wert deney 2.txt
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.include"m8def.inc"
;Seven Segment connected to portD
.equ segA = 0
.equ segB = 1
.equ segC = 3
.equ segD = 2
.equ segE = 7
.equ segF = 5
.equ segG = 6
.equ segP = 4
; Portb 4,5 connected to Seven segment common pins (common Anode)
.equ DispL = 4
.equ DispR = 5
.DSEG
rakam: .byte 1
.CSEG
.org 0
; Setting Stack
ldi r16,low (RAMEND)
out spl,r16
ldi r16,high (RAMEND)
out sph,r16
; Setup ports
ldi r16,255
out ddrd,r16 ;Portd Hepsi out
;sbi ddrb,DispL
;sbi portb,DispL ;display se鏼e
sbi ddrb,DispR
sbi portb,DispR ;display se鏼e
;initialize others
clr r16
sts rakam,r16
;main function
Main:
rcall sayilar
rjmp Main
sayilar:
rcall set_disp_num
rcall delay
lds r16,rakam
inc r16
cpi r16,10
breq sayilar_sil
rjmp sayilar_cik
sayilar_sil:
clr r16
sayilar_cik:
sts rakam,r16
ret
set_disp_num:
;r17 de num
ldi zl,low(2*numtable)
ldi zh,high(2*numtable)
push r16
add zl,r16 ; Add low byte
ldi r16,0
adc zh,r16 ; Add with carry high byte
lpm r16,z
out portd,r16
pop r16
ret
numtable:
.db 80,245,56,176,149,146,18,244,16,144
delay:
; ; -----------------------------
; delaying 1439970 cycles:
ldi R29, $05
WGLOOP0: ldi R30, $CE
WGLOOP1: ldi R31, $E8
WGLOOP2: dec R31
brne WGLOOP2
dec R30
brne WGLOOP1
dec R29
brne WGLOOP0
; -----------------------------
; delaying 30 cycles:
ldi R29, $0A
WGLOOP3: dec R29
brne WGLOOP3
; =============================
;
ret
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