hwinit_dm270.s.org

Embeded bootloader (rrload by ridgerun) for TI linux based platform v5.36

//
// File: hwinit_dm270.S
//
// Common portions of setup, head (rrload) and head (linux)
//
// Contains the necessary h/w setup specific to the TI DM270 EVM board.
//
// Derived from setup_dsc21.S, by RidgeRun, Inc.
// 09/26/02 Todd Fischer
//
//  This program is free software; you can redistribute  it and/or modify it
//  under  the terms of  the GNU General  Public License as published by the
//  Free Software Foundation;  either version 2 of the  License, or (at your
//  option) any later version.
//
//  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
//  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
//  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
//  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
//  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
//  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
//  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
//  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//  You should have received a copy of the  GNU General Public License along
//  with this program; if not, write  to the Free Software Foundation, Inc.,
//  675 Mass Ave, Cambridge, MA 02139, USA.

#include "memconfig.h"
#include "dm270-registers.h"
	
	.global hw_ini
	// Save lr so we can return
hw_ini:	mov r9, lr
	      
        // Initialize the board's clocks.
        bl clock_ini

        // Pause to let the PPLs lock
        mov  r1, #0xFF00
wloop:  subs r1, r1, #1
        bne  wloop


#if defined(BSPCONF_DM270_INGENIENT_MDV4100)
	// Initialize Pre GIO settings
	bl gio_ini
#endif

#if defined(BSPCONF_DM270_INGENIENT_TOKRA)
	// Initialize Pre GIO settings
	bl gio_ini
#endif        
        
	// Initialize board's memory controller
        bl memcntl_ini

        // Initialize board's SDRAM controller
        bl sdram_ini

        // Initialize board's HPI memory
        bl dsp_ini

        // Initialize UART 0
        bl uart0_ini

#if defined(BSPCONF_DM270_INGENIENT_MP4900)
        // Enable CS8900 LAN chip
	#if !defined(CADENUX_DM270_PMP)
        	bl lan_ini
	#endif
#endif
                
#if defined(BSPCONF_DM270_INGENIENT_MDV4100)
        // Enable CS8900 LAN chip
        bl lan_ini
#endif
        		
        bl clr_cmdline

done_hwinit:
	mov lr, r9   	
	mov pc, lr

// **********************
// Macro regw(add,data)
// **********************
        .macro regw, reg_add, reg_data
        ldr r0, =\reg_add
        ldr r1, =\reg_data
        strh r1, [r0]       
        .endm
                
// **********************
// Macro regr(add,data)
// **********************
        .macro regr, reg_add, reg_data
        ldr r0, =\reg_add
        ldrh \reg_data, [r0]       
        .endm
                
// **********************
// Macro short_wait()
// **********************
        .macro short_wait
	nop
	nop
	nop
	nop
        .endm
                
// **************************************
// Clear out linux command line override.
// (see __KernCommandLineOverride of kernel's setup.c)        
// **************************************
clr_cmdline:            
        regw CMDLINEOVERRIDE, NULL
        mov  pc, lr
        
// **************************************
// Setup on-board flash.
// **************************************
flash:          
        regw EXBC_CS0CTRL1, EXBC_CS0CTRL1_DATA
        regw EXBC_CS0CTRL2, EXBC_CS0CTRL1_DATA
        mov  pc, lr
                
// **************************************
// CLOCK controller initialize
// **************************************
clock_ini:
	regw CLOCKC_MOD0, MOD0_DATA_1	/* ARM core clock enable */
	regw CLOCKC_CLKC, CLKC_DATA	/* set external clock and select MXI */
	regw CLOCKC_BYP,  BYPON_DATA    /* bypass PLLs until they are stable */
	regw CLOCKC_PLLA, PLLA_DATA	/* prescale */

_check_plla:
	regr CLOCKC_PLLA, r1
	mov r2, #1
	cmps r2, r1, lsr #15
	bne _check_plla

	short_wait
	regw CLOCKC_PLLB, PLLB_DATA	/* prescale */

_check_pllb:
	regr CLOCKC_PLLB, r1
	mov r2, #1
	cmps r2, r1, lsr #15
	bne _check_pllb

	short_wait
	regw CLOCKC_CLKC, CLKC_DATA	/* clock inverse and source select */
        regw CLOCKC_SEL,  SEL_DATA
	regw CLOCKC_DIV,  DIV_DATA	/* ARM, SDRAM_CLK/2 */
	regw CLOCKC_BYP,  BYPOFF_DATA	/* not BYPASS for all */
	regw CLOCKC_MOD0, MOD0_DATA_2	/* All enable except for CEHIF */
	regw CLOCKC_MOD1, MOD1_DATA	/* All enable */
	regw CLOCKC_MOD2, MOD2_DATA	/* All enable */
					
#if defined(CADENUX_DM270_PMP)
	short_wait 
	regw  CLOCKC_OSEL,  OSEL_DATA   /* clock source select    */
	regw  CLOCKC_O0DIV, O0DIV_DATA  /* PLD clock 54MHz   	*/
	regw  CLOCKC_O1DIV, O1DIV_DATA  /* (set value+1)*2=4,SDRAM(108Mhz)/4= 27Mhz */
#endif


        mov  pc, lr
    	    
// *******************************************************
// Memory Controller initialize
// *******************************************************

memcntl_ini:
	regw EXBC_CS1CTRL1A, EXBC_CS1CTRL1A_DATA
	regw EXBC_CS1CTRL1B, EXBC_CS1CTRL1B_DATA
	regw EXBC_CS1CTRL2, EXBC_CS1CTRL2_DATA
	regw EXBC_CS2CTRL1, EXBC_CS2CTRL1_DATA
	regw EXBC_CS3CTRL1, EXBC_CS3CTRL1_DATA
	regw EXBC_CS2CTRL2, EXBC_CS2CTRL2_DATA
	regw EXBC_CS3CTRL2, EXBC_CS3CTRL2_DATA
	regw EXBC_CS4CTRL1, EXBC_CS4CTRL1_DATA
	regw EXBC_CS4CTRL2, EXBC_CS4CTRL2_DATA
	regw EXBC_BUSCTRL, EXBC_BUSCTRL_DATA
	regw EXBC_BUSRLS, EXBC_BUSRLS_DATA
	regw EXBC_DPSTR0, EXBC_DPSTR0_DATA
	regw EXBC_DPSTR1, EXBC_DPSTR1_DATA
	regw EXBC_DPSTR2, EXBC_DPSTR2_DATA
	regw EXBC_DPSTR3, EXBC_DPSTR3_DATA
	regw EXBC_DPSTR4, EXBC_DPSTR4_DATA
	regw EXBC_DPSTR5, EXBC_DPSTR5_DATA
	regw EXBC_TEST,EXBC_TEST_DATA
        mov  pc, lr
 
// *******************************************************
// SDRAM initialize  (and SDRAM precharge)
// *******************************************************

sdram_ini:
	regw SDRAMC_MODE, SDMODE_DATA	/* 32bitx1 */
	regw SDRAMC_REFCTL, SDREF_DATA	/* RefEn (0x40+1)*8clocks */
	regw SDRAMC_MODE, SDCNT_DATA1
	regw SDRAMC_MODE, SDCNT_DATA2
	regw SDRAMC_MODE, SDCNT_DATA2
	regw SDRAMC_MODE, SDCNT_DATA2
	regw SDRAMC_MODE, SDCNT_DATA2
	regw SDRAMC_MODE, SDCNT_DATA2
	regw SDRAMC_MODE, SDCNT_DATA2
	regw SDRAMC_MODE, SDCNT_DATA2
	regw SDRAMC_MODE, SDCNT_DATA2
	regw SDRAMC_MODE, SDCNT_DATA3

	// set priority access

#if defined(BSPCONF_DM270_INGENIENT)
	regw SDRAMC_SDPRTY9,  SDRAMC_SDPRTY9_DATA
	regw SDRAMC_SDPRTY10, SDRAMC_SDPRTY10_DATA
	regw SDRAMC_PRTYON,   SDRAMC_PRTYON_DATA
#endif
	mov  pc, lr

// *******************************************************
// DSP (HPI memory) initialize
// *******************************************************

dsp_ini:
	regw DSP_HPIB_CTL, DSP_RESET_DATA  /* DSP Reset */
	short_wait
	regw DSP_HPIB_CTL, DSP_NORMAL_DATA /* DSP Normal */
	short_wait
	regw DSP_HPIB_CTL, DSP_INT0_DATA   /* INT0 establish */
	mov  pc, lr

// *******************************************************
// UART 0 initialize
// *******************************************************

uart0_ini: 
        regw (UART0_REGISTER_BASE + UART_RFCR), UART_CONST_FIFO_CLEAR
        regw (UART0_REGISTER_BASE + UART_TFCR), UART_CONST_FIFO_CLEAR
        regw (UART0_REGISTER_BASE + UART_LCR),  0x0000
        regw (UART0_REGISTER_BASE + UART_RFCR), UART_TRIGGER_LEVEL_01
        regw (UART0_REGISTER_BASE + UART_TFCR), UART_TRIGGER_LEVEL_16
        regw (UART0_REGISTER_BASE + UART_BRSR), UART_BAUD_115200
        regw (UART0_REGISTER_BASE + UART_MSR),  UART_MODE_1_INIT
	mov  pc, lr

// **************************************
// Delay 1 ms
// **************************************

#if defined(BSPCONF_DM270_INGENIENT_TOKRA)
delay_1ms:
	ldr	r1, =47250		@94.5 MHz, 2 cycle loop
wloop2:
	subs	r1, r1, #1
	bne	wloop2

	mov	pc, lr
#endif
        
// *******************************************************
// GIO Initialize
// *******************************************************     
 
#if defined(BSPCONF_DM270_INGENIENT_TOKRA)
gio_ini:
	mov	r3, lr
	regw	GIO_BITSET0, GIO_BITSET0_DATA
	regw	GIO_BITCLR0, GIO_BITCLR0_DATA
	regw	GIO_DIR0, GIO_DIR0_DATA
	bl	delay_1ms

	regw	GIO_BITSET1, GIO_BITSET1_DATA
	regw	GIO_BITCLR1, GIO_BITCLR1_DATA
	regw	GIO_DIR1, GIO_DIR1_DATA
	bl	delay_1ms

	regw	GIO_BITSET2, GIO_BITSET2_DATA
	regw	GIO_BITCLR2, GIO_BITCLR2_DATA
	regw	GIO_DIR2, GIO_DIR2_DATA

// Wait for FX2 to set IDE_IDLE low, then we can access the hard drive
	ldr	r0, =GIO_BITSET0
	mov	r1, #0x4000		@ bit 14 mask
idle_wait:
	ldrh	r2, [r0]		@ r2 = BITSET0 value
	and	r2, r2, r1		@ mask off all but bit 14
	tst	r2, r2
	bne	idle_wait		@ keep looping until zero

// Set IDE_LOCAL low so we can access the hard drive
	regw	GIO_BITCLR0, GIO_BITCLR0_DATA2

	mov	pc, r3
#endif
        
#if defined(BSPCONF_DM270_INGENIENT_MDV4100)
gio_ini:
	mov	r3, lr
	regw	GIO_DIR1, GIO_DIR1_DATA
	regw	GIO_BITCLR1, GIO_BITCLR1_DATA
	mov	pc, r3
#endif

// *******************************************************
// CS8900 initialize
// *******************************************************

#if defined(BSPCONF_DM270_INGENIENT_MP4900)
lan_ini: 
	mov 	r3, lr
        regw    GIO_DIR0,    GIO_DIR0_DATA 
	regw    GIO_BITSET0, GIO_BITSET0_DATA
        regw    GIO_BITCLR0, GIO_BITCLR0_DATA 
      	mov     pc, lr
#endif
        
#if defined(BSPCONF_DM270_INGENIENT_MDV4100)
lan_ini: 
	mov 	r3, lr
        regw    GIO_DIR0,    GIO_DIR0_DATA
        regw    GIO_BITSET0, GIO_BITSET0_DATA
        regw    GIO_BITCLR0, GIO_BITCLR0_DATA 
      	mov     pc, lr
#endif

CMDLINEOVERRIDE:  .word 0x01000000
NULL:             .word 0x0000
MEMTEST_DATA:     .long 0xa5a5a5a5