setup_dm270.s

Embeded bootloader (rrload by ridgerun) for TI linux based platform v5.36

//
// File: setup_dm270.S
//
// (Derived from head-arm-atmel.S and Boot.asm)
//
// Contains the necessary h/w setup specific to the TI DM270 EVM board.
//
// Copyright (C) 2002 RidgeRun, Inc.
// Author: RidgeRun, Inc  <[e-mail]>
//  - Derived from setup_dsc21.S, 9/6/02, Gregory Nutt
//  - Derived from setup_dsc25.S, 2/19/03, Gregory Nutt
//
//  This program is free software; you can redistribute  it and/or modify it
//  under  the terms of  the GNU General  Public License as published by the
//  Free Software Foundation;  either version 2 of the  License, or (at your
//  option) any later version.
//
//  THIS  SOFTWARE  IS  PROVIDED  ``AS  IS''  AND   ANY  EXPRESS  OR IMPLIED
//  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
//  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
//  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
//  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
//  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
//  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
//  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//  You should have received a copy of the  GNU General Public License along
//  with this program; if not, write  to the Free Software Foundation, Inc.,
//  675 Mass Ave, Cambridge, MA 02139, USA.
//
// Please report all bugs/problems to the author or <[e-mail]>
//
// key: RRGPLCR (do not remove)
//

#include "memconfig.h"
        
#define I_BIT        0x80
#define F_BIT        0x40
#define ARM_MODE_SVC 0x13

        .text
        .align
_start:
        // Turn off IRQ/FIQ and put into service mode.
        mov r0, #(ARM_MODE_SVC | I_BIT | F_BIT)
        msr cpsr, r0

	// Initialize the hardware
	bl hw_ini	

        // Setup Stack in IRAM for rrload
	// This assumes rrload will be loaded using JTAG 

	ldr sp, =0x08000

#if 0
        // memory test - fill and check
	
	ldr r10,=BSPCONF_SDRAM_BASE + BSPCONF_SDRAM_SIZE @ ending address
        ldr r9, =BSPCONF_SDRAM_BASE @ starting address
        ldr r8, MEMTEST_DATA

	mov r7, r10  	
	mov r5, r9
1:	eor r4, r5, r8 @ stored value is address XOR with alternating 1/0s
	str r4, [r5]
	ldr r3, [r5]
	cmp r4, r3
badwrite:
	bne badwrite
	add r5, r5, #4
	cmp r5, r7
        bcc 1b

        // check again
	
	mov r7, r10  	
	mov r5, r9
2:	eor r4, r5, r8 @ stored value is address XOR with alternating 1/0s
	ldr r3, [r5]
	cmp r4, r3
badread:
	bne badread
	add r5, r5, #4
	cmp r5, r7
        bcc 2b	
	
memtest_passed:
	b memtest_passed

#endif
        	
forever:                
        b   forever

MEMTEST_DATA:   .long 0xa5a5a5a5