dm270-registers.h

Embeded bootloader (rrload by ridgerun) for TI linux based platform v5.36

#define SDCNT_DATA1             (SDMODE_DATA | 0x0002)
#define SDCNT_DATA2             (SDMODE_DATA | 0x0004)
#define SDCNT_DATA3             (SDMODE_DATA | 0x0001)

#else

#error Unknown BSPCONF_SDRAM_TYPE

#endif

#if defined(BSPCONF_DM270_INGENIENT)
#  define SDRAMC_SDPRTY9_DATA   0x0001
#  define SDRAMC_SDPRTY10_DATA  0x0002
#  define SDRAMC_PRTYON_DATA    0x0001
#else
#  define SDRAMC_REFCTL_DATA    0x0000
#  define SDRAMC_SDPRTY1_DATA   0x0001
#  define SDRAMC_SDPRTY2_DATA   0x0002
#  define SDRAMC_SDPRTY3_DATA   0x0004
#  define SDRAMC_SDPRTY4_DATA   0x0008
#  define SDRAMC_SDPRTY5_DATA   0x0010
#  define SDRAMC_SDPRTY6_DATA   0x0020
#  define SDRAMC_SDPRTY7_DATA   0x0040
#  define SDRAMC_SDPRTY8_DATA   0x0080
#  define SDRAMC_SDPRTY9_DATA   0x0100
#  define SDRAMC_SDPRTY10_DATA  0x0200
#  define SDRAMC_PRTYON_DATA    0x0000
#endif

/* DSP Controller */

#define DSP_HPIB_CTL            0x00030600 /* HPIB Control Register */
#define DSP_HPIB_STAT           0x00030602 /* HPIB Status Register */

/* DSP Controller Initial Settings */

#define DSP_RESET_DATA          0x0689
#define DSP_NORMAL_DATA         0x0789
#define DSP_INT0_DATA           0x0709

/* External Bus */

#define EXBC_CS0CTRL1           0x00030a00 
#define EXBC_CS0CTRL2           0x00030a02
#define EXBC_CS1CTRL1A          0x00030a04
#define EXBC_CS1CTRL1B          0x00030a06
#define EXBC_CS1CTRL2           0x00030a08
#define EXBC_CS2CTRL1           0x00030a0a
#define EXBC_CS3CTRL1           0x00030a0e
#define EXBC_CS2CTRL2           0x00030a0c
#define EXBC_CS3CTRL2           0x00030a10
#define EXBC_CS4CTRL1           0x00030a12
#define EXBC_CS4CTRL2           0x00030a14
#define EXBC_BUSCTRL            0x00030a16
#define EXBC_BUSRLS             0x00030a18
#define EXBC_CFCTRL1            0x00030a1a
#define EXBC_CFCTRL2            0x00030a1c
#define EXBC_SMCTRL             0x00030a1e
#define EXBC_BUSINTEN           0x00030a20
#define EXBC_BUSSTS             0x00030a24
#define EXBC_BUSWAITMD          0x00030a26
#define EXBC_ECC1CP             0x00030a28
#define EXBC_ECC1LP             0x00030a2a
#define EXBC_ECC2CP             0x00030a2c
#define EXBC_ECC2LP             0x00030a2e
#define EXBC_ECCCLR             0x00030a30
#define EXBC_PAGESZ             0x00030a32
#define EXBC_IMGDSPDEST         0x00030a34
#define EXBC_PRIORCTL           0x00030a36
#define EXBC_SOURCEADD1         0x00030a38
#define EXBC_SOURCEADD2         0x00030a3a
#define EXBC_DESTADD1           0x00030a3c
#define EXBC_DESTADD2           0x00030a3e
#define EXBC_DMASIZE            0x00030a40
#define EXBC_DMADEVSEL          0x00030a42
#define EXBC_DMACTL             0x00030a44
#define EXBC_IMGDSPADD1         0x00030a46
#define EXBC_IMGDSPADD2         0x00030a48
#define EXBC_DPSTR0             0x00030a4a
#define EXBC_DPSTR1             0x00030a4c
#define EXBC_DPSTR2             0x00030a4e
#define EXBC_DPSTR3             0x00030a50
#define EXBC_DPSTR4             0x00030a52
#define EXBC_DPSTR5             0x00030a54
#define EXBC_TEST               0x00030a56

/* External Bus Initial Settings */

#if defined(BSPCONF_DM270_INGENIENT)
	#if defined(CADENUX_DM270_PMP)
		#  define EXBC_CS0CTRL1_DATA    0x889A
		#  define EXBC_CS0CTRL2_DATA    0x1110 /* IDLE=1 OE=1   WE=1   CE=0 */
		#  define EXBC_CS1CTRL1A_DATA   0x1213
		#  define EXBC_CS1CTRL1B_DATA   0x0e0e 
		#  define EXBC_CS1CTRL2_DATA    0x1330 /* IDLE=1 OE=2   WE=2   CE=0 */
		#  define EXBC_CS2CTRL1_DATA    0x3207
		#  define EXBC_CS2CTRL2_DATA    0x1129
		#  define EXBC_CS3CTRL1_DATA    0x77ab
		#  define EXBC_CS3CTRL2_DATA    0x5220 
		#  define EXBC_CS4CTRL1_DATA    0x88ef 
		#  define EXBC_CS4CTRL2_DATA    0x5220 /* LO 16bit IDLE=3 OE=1 WE=1 CE=0 */
	#else
		#  define EXBC_CS0CTRL1_DATA    0x889A
		#  define EXBC_CS0CTRL2_DATA    0x1110 /* IDLE=1 OE=1   WE=1   CE=0 */
		#  define EXBC_CS1CTRL1A_DATA   0x1415 /* CE=21w CYC=22w */
		#  define EXBC_CS1CTRL1B_DATA   0x1109 /* OE=18w WE=10w */
		#  define EXBC_CS1CTRL2_DATA    0x1220 /* IDLE=1 OE=2   WE=2   CE=0 */
		#  define EXBC_CS2CTRL1_DATA    0x3207
		#  define EXBC_CS3CTRL1_DATA    0x889A
		#  define EXBC_CS2CTRL2_DATA    0x1129
		#  define EXBC_CS3CTRL2_DATA    0x5110 /* WD=16b  IDLE=1 OE=1   CE=0 */
		#  define EXBC_CS4CTRL1_DATA    0xCCDE /* OE=13w  WE=13w  CE=14w CYC=15w */
		#  define EXBC_CS4CTRL2_DATA    0x7110 /* LO 16bit IDLE=3 OE=1 WE=1 CE=0 */
	#endif
#else
	#  define EXBC_CS0CTRL1_DATA    0x5877 /* OE=6w  WE=9w  CE=8w  CYC=8w */
	#  define EXBC_CS0CTRL2_DATA    0x3110 /* IDLE=3 OE=1   WE=1   CE=0 */
	#  define EXBC_CS1CTRL1A_DATA   0x1415 /* CE=21w CYC=22w */
	#  define EXBC_CS1CTRL1B_DATA   0x1109 /* OE=18w WE=10w */
	#  define EXBC_CS1CTRL2_DATA    0x1220 /* IDLE=1 OE=2   WE=2   CE=0 */
	#  define EXBC_CS2CTRL1_DATA    0x110a /* OE=2w  WE=2w  rsvd   CYC=11w */
	#  define EXBC_CS2CTRL2_DATA    0x1129 /* OE=2w  WE=2w  CE=3w  CYC=10w */
	#  define EXBC_CS3CTRL1_DATA    0x8899 /* IDLE=0 OE=8   WE=9   RE=12 */
	#  define EXBC_CS3CTRL2_DATA    0x1110 /* WD=8b  IDLE=1 OE=1   CE=0 */
	#  define EXBC_CS4CTRL1_DATA    0xCCDE /* OE=13w  WE=13w  CE=14w CYC=15w */
	#  define EXBC_CS4CTRL2_DATA    0x7110 /* LO 16bit IDLE=3 OE=1 WE=1 CE=0 */
	#  define EXBC_BUSCTRL_DATA     0x0000 /* Ext wait invalid */
#endif
#define EXBC_BUSCTRL_DATA       0x0000 /* Ext wait invalid */
#define EXBC_BUSRLS_DATA        0x0000 /* normal not-open not-open */
#define EXBC_CFCTRL1_DATA       0x0000 /* CF card selected */
#define EXBC_CFCTRL2_DATA       0x0000 /* CF 16bit low output */
#if defined(CADENUX_DM270_PMP)
	#define EXBC_SMCTRL_DATA        0x0000 
#else
	#define EXBC_SMCTRL_DATA        0x0001 /* SCE low level */
#endif
#define EXBC_BUSINTEN_DATA      0x0000 /* CF low-high disabled */

#if defined(CADENUX_DM270_PMP)
	#define EXBC_BUSSTS_DATA        0x000f /* IOIS16+CFWAIT+CFRDY shown */
#else
	#define EXBC_BUSSTS_DATA        0x0007 /* IOIS16+CFWAIT+CFRDY shown */
#endif

#define EXBC_BUSWAITMD_DATA     0x0000 /* CF RDY/-BSY connected */
#define EXBC_ECC1CP_DATA        0x00ff /* SM ECC CP */
#define EXBC_ECC1LP_DATA        0xffff /* SM ECC LP */
#define EXBC_ECC2CP_DATA        0x00ff /* SM ECC CP */
#define EXBC_ECC2LP_DATA        0xffff /* SM ECC LP */
#define EXBC_ECCCLR_DATA        0x0000 /* SM ECC clear */
#define EXBC_PAGESZ_DATA        0x0001 /* SM page size = 256+8byte/page */
#define EXBC_IMGDSPDEST_DATA    0x0000 /* IMG source=CS0 dest=CS0 */
#define EXBC_PRIORCTL_DATA      0x001b /* Priorities */
#define EXBC_SOURCEADD1_DATA    0x0000 /* DMA addr incr + upper address */
#define EXBC_SOURCEADD2_DATA    0x0000 /* DMA lower address */
#define EXBC_DESTADD1_DATA      0x0000 /* DMA addr incr + upper address */
#define EXBC_DESTADD2_DATA      0x0000 /* DMA lower address */
#define EXBC_DMASIZE_DATA       0x0000 /* DMA size of transfer */
#define EXBC_DMADEVSEL_DATA     0x0000 /* DMA src=CS0 dest=CS0 */
#define EXBC_DMACTL_DATA        0x0000 /* DMA no switching, not started */
#define EXBC_IMGDSPADD1_DATA    0x0000 /* IMG upper address */
#define EXBC_IMGDSPADD2_DATA    0x0000 /* IMG lower addres */

// Physical memory map

#if 1
	#if defined(CADENUX_DM270_PMP)
		#define EXBC_DPSTR0_DATA        0x0021 /* CS0 (FLASH) 10:0000-210:0000 */
		#define EXBC_DPSTR1_DATA        0x0061 /* SDRAM      210:0000-610:0000 */
		#define EXBC_DPSTR2_DATA        0x0066 /* CS1 (CF)   610:0000-660:0000 */
		#define EXBC_DPSTR3_DATA        0x006a /* CS2 (SM)   660:0000-6a0:0000 */
		#define EXBC_DPSTR4_DATA        0x0082 /* CS3        6a0:0000-820:0000 */
		#define EXBC_DPSTR5_DATA        0x0083 /* CS4 ether  820:0000-830:0000 */
	#else
		#define EXBC_DPSTR0_DATA        0x0021 /* CS0 (FLASH) 10:0000-210:0000 */
		#define EXBC_DPSTR1_DATA        0x0061 /* SDRAM      210:0000-610:0000 */
		#define EXBC_DPSTR2_DATA        0x0066 /* CS1 (CF)   610:0000-660:0000 */
		#define EXBC_DPSTR3_DATA        0x006a /* CS2 (SM)   660:0000-6a0:0000 */
		#define EXBC_DPSTR4_DATA        0x006b /* CS3        6a0:0000-6b0:0000 */
		#define EXBC_DPSTR5_DATA        0x006c /* CS4 ether  6b0:0000-6c0:0000 */
	#endif
#else
	#define EXBC_DPSTR0_DATA        0x0021 /* CS0 (FLASH) 10:0000-210:0000 */
	#define EXBC_DPSTR1_DATA        0x0041 /* SDRAM      210:0000-410:0000 */
	#define EXBC_DPSTR2_DATA        0x0081 /* CS1 (CF)   410:0000-810:0000 */
	#define EXBC_DPSTR3_DATA        0x00a1 /* CS2 (SM)   810:0000-a10:0000 */
	#define EXBC_DPSTR4_DATA        0x00c1 /* CS3        a10:0000-c10:0000 */
	#define EXBC_DPSTR5_DATA        0x00ef /* CS4 ether  c10:0000-e10:0000 */
#endif

#define EXBC_TEST_DATA          0x0000 /* Normal mode */

/* UART Registers */

/* Register Offsets */

#define UART_DTRR              0     /* Data Transmit/Receive Register */
#define UART_BRSR              2     /* Bit Rate Set Register */
#define UART_MSR               4     /* Mode Set Register */
#define UART_RFCR              6     /* Reception FIFO Control Register */
#define UART_TFCR              8     /* Transmission FIFO Control Register */
#define UART_LCR              10     /* Line Control Register */
#define UART_SR               12     /* Status Register */

/* UART status */

#define UART_RX_FIFO_LEVEL    0x0800 /* RX FIFO >= trigger level */
#define UART_TX_FIFO_LEVEL    0x0400 /* TX FIFO < trigger level */
#define UART_ERROR            0x0200 /* Error RX FIFO */
#define UART_TIMEOUT          0x0100 /* Timeout */
#define UART_RX_FIFO_NOEMPTY  0x0004 /* RX FIFO is not empty */
#define UART_TX_FIFO_EMPTY    0x0002 /* TX FIFO is empty */
#define UART_TX_EMPTY         0x0001 /* both RX&TX FIFO shift-reg empty */

/* FIFO trigger level */

#define UART_TRIGGER_LEVEL_01 0x0000 /*  1-byte */
#define UART_TRIGGER_LEVEL_04 0x0100 /*  4-byte */
#define UART_TRIGGER_LEVEL_08 0x0200 /*  8-byte */
#define UART_TRIGGER_LEVEL_16 0x0300 /* 16-byte */
#define UART_TRIGGER_LEVEL_24 0x0400 /* 24-byte */
#define UART_TRIGGER_LEVEL_32 0x0500 /* 32-byte */

#define UART_TRIGGER_LEVEL_1_INIT UART_TRIGGER_LEVEL_01

/* UART mode settings */

#define UART_RXFIFO_INT       0x8000 /* Enable receiver trigger interrupt */
#define UART_TXFIFO_INT       0x4000 /* Enable transmitter trigger interrupt */
#define UART_RCVERR_INT       0x2000 /* Enable receiving error interrupt */
#define UART_NOTIMEOUT_INT    0x0000 /* Disable timeout interrupt */
#define UART_TIMEOUT_3WORD    0x0400 /* Enable timeout interrupt with 3-word */
#define UART_TIMEOUT_7WORD    0x0800 /* Enable timeout interrupt with 7-word */
#define UART_TIMEOUT_15WORD   0x0c00 /* Enable timeout interrupt with 15-word */
#define UART_NOPARITY         0x0000 /* No-parity */
#define UART_ODDPARITY        0x0018 /* Odd parity */
#define UART_EVENPARITY       0x0010 /* Even parity */
#define UART_STOPBIT_1        0x0000 /* Stop bit = 1bit */
#define UART_STOPBIT_2        0x0004 /* Stop bit = 2bit */
#define UART_DATABIT_7        0x0001 /* Data bit = 7bit */
#define UART_DATABIT_8        0x0000 /* Data bit = 8bit */

#define UART_MODE_1_INIT      (UART_NOPARITY | UART_STOPBIT_1 | UART_DATABIT_8)

/* UART error bits */

#define UART_DATA_VALID       0x10   /* Data is valid */
#define UART_BREAK_FLAG       0x08   /* Break detected */
#define UART_FRAME_ERROR      0x04   /* Frame error is detected */
#define UART_OVERRUN          0x02   /* Overrun detected */
#define UART_PARITY_ERROR     0x01   /* Parity error detected */

/* the following formulas to calculate the baud 
 * rate divisor are only true if CLOCK_CLKC is 
 * set to use the ARM for the clock rate
 */

#if (CLKC_DATA & 0x0200)
# define UART_CLK 27000000 /* 27 Mhz MXI used for UART0 clock */
#else
# define UART_CLK (ARM_CLK)
#endif

/* baud rate = UART_CLK / 16 / (VALUE+1)
 * VALUE = (UART_CLK / 16 / baud_rate ) - 1
 */

#define UART_BAUD_2400    ((((UART_CLK / 16) / 2400  ) - 1))
#define UART_BAUD_4800    ((((UART_CLK / 16) / 4800  ) - 1))
#define UART_BAUD_9600    ((((UART_CLK / 16) / 9600  ) - 1))
#define UART_BAUD_14400   ((((UART_CLK / 16) / 14400 ) - 1))
#define UART_BAUD_19200   ((((UART_CLK / 16) / 19200 ) - 1))
#define UART_BAUD_28800   ((((UART_CLK / 16) / 28800 ) - 1))
#define UART_BAUD_38400   ((((UART_CLK / 16) / 38400 ) - 1))
#define UART_BAUD_57600   ((((UART_CLK / 16) / 57600 ) - 1))
#define UART_BAUD_115200  ((((UART_CLK / 16) / 115200) - 1))
#define UART_BAUD_230400  ((((UART_CLK / 16) / 230400) - 1))
#define UART_BAUD_460800  ((((UART_CLK / 16) / 460800) - 1))
#define UART_BAUD_921600  ((((UART_CLK / 16) / 921600) - 1))

/* Synonyms */

#define UART_CONST_FIFO_CLEAR     0x8000 /* RX/TX FIFO clear bit (RFCR/TFCR) */
#define UART_CONST_WORDCOUNT_MASK 0x003f /* Word count mask (RFCR/TFCR) */
#define UART_CONST_BREAK          0x0100 /* Break mask (LCR) */
#define UART_CONST_TX_EMPTY       0x0001 /* Empty bit (TX) */
#define UART_CONST_RX_READ_VALID  0x1000

/* I-Cache */

#define DM270_ICACHE_ICAMODE    0x00030e00

/* I-Cache Settings */

#define DM270_ICAMODE_ICAENB    0x0001 /* Cache enable bit */
#define DM270_ICAMODE_ICADIS    0x0000 /* Cache disable */
#define DM270_ICAMODE_ICACLR    0x0002 /* Cache clear bit */
#define DM270_ICAMODE_REQ4W     0x0100 /* 4 word burst access request */

#endif /* __RRLOAD_DM270_REGISTER_H */