disasm-arm.cc.svn-base

Google浏览器V8内核代码

        }
        case 1: {
          if (instr->Bit(22) == 0) {
            Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
          } else {
            Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
          }
          break;
        }
        case 2: {
          if (instr->Bit(22) == 0) {
            Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
          } else {
            Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
          }
          break;
        }
        case 3: {
          if (instr->Bit(22) == 0) {
            Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
          } else {
            Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
          }
          break;
        }
        default: {
          // The PU field is a 2-bit field.
          UNREACHABLE();
          break;
        }
      }
      return;
    }
  } else {
    switch (instr->OpcodeField()) {
      case AND: {
        Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
        break;
      }
      case EOR: {
        Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
        break;
      }
      case SUB: {
        Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
        break;
      }
      case RSB: {
        Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
        break;
      }
      case ADD: {
        Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
        break;
      }
      case ADC: {
        Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
        break;
      }
      case SBC: {
        Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
        break;
      }
      case RSC: {
        Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
        break;
      }
      case TST: {
        if (instr->HasS()) {
          Format(instr, "tst'cond 'rn, 'shift_rm");
        } else {
          Unknown(instr);  // not used by V8
          return;
        }
        break;
      }
      case TEQ: {
        if (instr->HasS()) {
          Format(instr, "teq'cond 'rn, 'shift_rm");
        } else {
          Unknown(instr);  // not used by V8
          return;
        }
        break;
      }
      case CMP: {
        if (instr->HasS()) {
          Format(instr, "cmp'cond 'rn, 'shift_rm");
        } else {
          Unknown(instr);  // not used by V8
          return;
        }
        break;
      }
      case CMN: {
        if (instr->HasS()) {
          Format(instr, "cmn'cond 'rn, 'shift_rm");
        } else {
          Unknown(instr);  // not used by V8
          return;
        }
        break;
      }
      case ORR: {
        Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
        break;
      }
      case MOV: {
        Format(instr, "mov'cond's 'rd, 'shift_rm");
        break;
      }
      case BIC: {
        Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
        break;
      }
      case MVN: {
        Format(instr, "mvn'cond's 'rd, 'shift_rm");
        break;
      }
      default: {
        // The Opcode field is a 4-bit field.
        UNREACHABLE();
        break;
      }
    }
  }
}


void Decoder::DecodeType1(Instr* instr) {
  switch (instr->OpcodeField()) {
    case AND: {
      Format(instr, "and'cond's 'rd, 'rn, 'imm");
      break;
    }
    case EOR: {
      Format(instr, "eor'cond's 'rd, 'rn, 'imm");
      break;
    }
    case SUB: {
      Format(instr, "sub'cond's 'rd, 'rn, 'imm");
      break;
    }
    case RSB: {
      Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
      break;
    }
    case ADD: {
      Format(instr, "add'cond's 'rd, 'rn, 'imm");
      break;
    }
    case ADC: {
      Format(instr, "adc'cond's 'rd, 'rn, 'imm");
      break;
    }
    case SBC: {
      Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
      break;
    }
    case RSC: {
      Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
      break;
    }
    case TST: {
      if (instr->HasS()) {
        Format(instr, "tst'cond 'rn, 'imm");
      } else {
        Unknown(instr);  // not used by V8
        return;
      }
      break;
    }
    case TEQ: {
      if (instr->HasS()) {
        Format(instr, "teq'cond 'rn, 'imm");
      } else {
        Unknown(instr);  // not used by V8
        return;
      }
      break;
    }
    case CMP: {
      if (instr->HasS()) {
        Format(instr, "cmp'cond 'rn, 'imm");
      } else {
        Unknown(instr);  // not used by V8
        return;
      }
      break;
    }
    case CMN: {
      if (instr->HasS()) {
        Format(instr, "cmn'cond 'rn, 'imm");
      } else {
        Unknown(instr);  // not used by V8
        return;
      }
      break;
    }
    case ORR: {
      Format(instr, "orr'cond's 'rd, 'rn, 'imm");
      break;
    }
    case MOV: {
      Format(instr, "mov'cond's 'rd, 'imm");
      break;
    }
    case BIC: {
      Format(instr, "bic'cond's 'rd, 'rn, 'imm");
      break;
    }
    case MVN: {
      Format(instr, "mvn'cond's 'rd, 'imm");
      break;
    }
    default: {
      // The Opcode field is a 4-bit field.
      UNREACHABLE();
      break;
    }
  }
}


void Decoder::DecodeType2(Instr* instr) {
  switch (instr->PUField()) {
    case 0: {
      if (instr->HasW()) {
        Unknown(instr);  // not used in V8
        return;
      }
      Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
      break;
    }
    case 1: {
      if (instr->HasW()) {
        Unknown(instr);  // not used in V8
        return;
      }
      Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
      break;
    }
    case 2: {
      Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
      break;
    }
    case 3: {
      Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
      break;
    }
    default: {
      // The PU field is a 2-bit field.
      UNREACHABLE();
      break;
    }
  }
}


void Decoder::DecodeType3(Instr* instr) {
  switch (instr->PUField()) {
    case 0: {
      ASSERT(!instr->HasW());
      Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
      break;
    }
    case 1: {
      ASSERT(!instr->HasW());
      Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
      break;
    }
    case 2: {
      Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
      break;
    }
    case 3: {
      Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
      break;
    }
    default: {
      // The PU field is a 2-bit field.
      UNREACHABLE();
      break;
    }
  }
}


void Decoder::DecodeType4(Instr* instr) {
  ASSERT(instr->Bit(22) == 0);  // Privileged mode currently not supported.
  if (instr->HasL()) {
    Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
  } else {
    Format(instr, "stm'cond'pu 'rn'w, 'rlist");
  }
}


void Decoder::DecodeType5(Instr* instr) {
  Format(instr, "b'l'cond 'target");
}


void Decoder::DecodeType6(Instr* instr) {
  // Coprocessor instructions currently not supported.
  Unknown(instr);
}


void Decoder::DecodeType7(Instr* instr) {
  if (instr->Bit(24) == 1) {
    Format(instr, "swi'cond 'swi");
  } else {
    // Coprocessor instructions currently not supported.
    Unknown(instr);
  }
}


// Disassemble the instruction at *instr_ptr into the output buffer.
int Decoder::InstructionDecode(byte* instr_ptr) {
  Instr* instr = Instr::At(instr_ptr);
  // Print raw instruction bytes.
  out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
                                       "%08x       ",
                                       instr->InstructionBits());
  if (instr->ConditionField() == special_condition) {
    Format(instr, "break 'msg");
    return Instr::kInstrSize;
  }
  switch (instr->TypeField()) {
    case 0: {
      DecodeType0(instr);
      break;
    }
    case 1: {
      DecodeType1(instr);
      break;
    }
    case 2: {
      DecodeType2(instr);
      break;
    }
    case 3: {
      DecodeType3(instr);
      break;
    }
    case 4: {
      DecodeType4(instr);
      break;
    }
    case 5: {
      DecodeType5(instr);
      break;
    }
    case 6: {
      DecodeType6(instr);
      break;
    }
    case 7: {
      DecodeType7(instr);
      break;
    }
    default: {
      // The type field is 3-bits in the ARM encoding.
      UNREACHABLE();
      break;
    }
  }
  return Instr::kInstrSize;
}


} }  // namespace assembler::arm



//------------------------------------------------------------------------------

namespace disasm {

static const char* reg_names[16] = {
  "r0", "r1", "r2" , "r3" , "r4" , "r5" , "r6" , "r7" ,
  "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc",
};


const char* NameConverter::NameOfAddress(byte* addr) const {
  static v8::internal::EmbeddedVector<char, 32> tmp_buffer;
  v8::internal::OS::SNPrintF(tmp_buffer, "%p", addr);
  return tmp_buffer.start();
}


const char* NameConverter::NameOfConstant(byte* addr) const {
  return NameOfAddress(addr);
}


const char* NameConverter::NameOfCPURegister(int reg) const {
  const char* result;
  if ((0 <= reg) && (reg < 16)) {
    result = reg_names[reg];
  } else {
    result = "noreg";
  }
  return result;
}


const char* NameConverter::NameOfXMMRegister(int reg) const {
  UNREACHABLE();  // ARM does not have any XMM registers
  return "noxmmreg";
}


const char* NameConverter::NameInCode(byte* addr) const {
  // The default name converter is called for unknown code. So we will not try
  // to access any memory.
  return "";
}


//------------------------------------------------------------------------------

static NameConverter defaultConverter;

Disassembler::Disassembler() : converter_(defaultConverter) {}


Disassembler::Disassembler(const NameConverter& converter)
    : converter_(converter) {}


Disassembler::~Disassembler() {}


int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
                                    byte* instruction) {
  assembler::arm::Decoder d(converter_, buffer);
  return d.InstructionDecode(instruction);
}


int Disassembler::ConstantPoolSizeAt(byte* instruction) {
  int instruction_bits = *(reinterpret_cast<int*>(instruction));
  if ((instruction_bits & 0xfff00000) == 0x03000000) {
    return instruction_bits & 0x0000ffff;
  } else {
    return -1;
  }
}


void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
  Disassembler d;
  for (byte* pc = begin; pc < end;) {
    v8::internal::EmbeddedVector<char, 128> buffer;
    buffer[0] = '\0';
    byte* prev_pc = pc;
    pc += d.InstructionDecode(buffer, pc);
    fprintf(f, "%p    %08x      %s\n",
            prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
  }
}


}  // namespace disasm