eth400.a51

DS80C400以太网物理链路层配置

           anl   a, #(80h or 40h)
           jnz   eth_ueh_release

           mov   a, r3                  ; restore and get frame length
           anl   a, #3fh
           mov   r3, a                  ; save HSB of frame length

           movx  a, @dptr
           inc   dptr

           ; check CRC error, MII error, collision seen, frame too long
           anl   a, #(20h or 08h or 02h or 01h)
           jnz   eth_ueh_release

           movx  a, @dptr                         ; MSB of status word
           ; check for length error, control frame, unsupported ctrl frame
           ; missed frame
           mov   B, a
           anl   a, #(80h or 20h or 04h or 02h or 01h)
           jnz   eth_ueh_release        ; bad bad bad frame!

           mov   a, B
           anl   a, #40h		        ; check for filter match
           jz    eth_ueh_release

           ; XXX Copy the packet into your buffer here.
           ; XXX r3:r2 contain the length of the packet,
           ; XXX dptr0 points to the beginning of the data.
           ; XXX Note that the buffer can wrap!

eth_ueh_release:
           ret


;****************************************************************************
;*
;* Function Name: ETH_Release
;*
;*   Description: Release resources.
;*
;*      Input(s): N/A
;*
;*    Outputs(s): N/A
;*
;****************************************************************************
ETH_Release:
           anl   BCUC, #0f0h          ; Clear bcuc command bits
           orl   BCUC, #BCU_INV_CURR  ; Write release command to bcuc SFR
           ret


;****************************************************************************
;*
;* Function Name: ETH_ProcessInterrupt
;*
;*   Description: ISR for Ethernet interrupt
;*
;*      Input(s): N/A
;*
;*    Outputs(s): N/A
;*
;*     Destroyed: Nothing.
;****************************************************************************
ETH_ProcessInterrupt:
           push  ACC
           mov   a, BCUC
           anl   a, #RIF			; Received data?
           jz    eth_pi_no_receive
           ; XXX Call your receive packet handler here.
           ; XXX Ensure it saves and restores all registers!
           ; XXX E.g.: acall ETH_ProcessPacket
eth_pi_no_receive:
           mov   a, BCUC
           anl   a, #TIF
           jz    eth_pi_exit		; Transmitted data?
           ; XXX If you keep track of a send in progress, here's the place
           ; XXX to clear the flag.
           ; XXX E.g.: clr   ds400_xmit
           anl    BCUC, #(not(TIF) and 0f0h) ; and NOOP command
           ; XXX If you keep transmit queue, send next packet from queue
           ; XXX E.g.: acall ETH_SendNextFromQueue
eth_pi_exit:
           pop   ACC
           reti


;****************************************************************************
;*
;* Function Name: ETH_EnableInterrupts
;*
;*   Description: Enable Ethernet transmit/receive interrupts.
;*          
;*
;*      Input(s): 
;*
;*    Outputs(s): 
;*                
;*     Destroyed:
;****************************************************************************
ETH_EnableInterrupts:
           ; XXX If you keep track of transmits in progress, clear
           ; XXX the flag here.
           ; XXX E.g.: clr   ds400_xmit
           anl   BCUC, #(not(RIF or TIF) and 0f0h) ; Clear interrupt flags
           setb  EIE.5                  ; Enable Ethernet activity interrupt
           clr   EAIP                   ; Set network interrupt priority low
           ret


;****************************************************************************
;*
;* Function Name: ETH_ReadMII
;*
;*   Description: Read MII register
;*
;*      Input(s): a -> register number, b -> PHY number
;*
;*    Outputs(s): r1:r0 -> contents of MII register
;*
;*         Notes: MII address Register (14h):
;*                31-16 -- reserved
;*                15-11 -- PHY address
;*                10-6  -- MII register
;*                5-2   -- reserved
;*                1     -- MII write
;*                0     -- MII busy
;*
;****************************************************************************
ETH_ReadMII:
           push  EIE
           clr   EIE.5

           mov   r7, a                       ; Save register number
           ; Wait until MII is not busy
eth_rmii_busy:
           mov   a, #CSR_MII_ADDR
           acall ETH_ReadCSR

           mov   a, r0
           jb    ACC.0, eth_rmii_busy

           clr   a
           mov   r3, a                       ; Reserved - always clear
           mov   r2, a

           mov   a, r7                       ; Restore register number
           rr    a
           rr    a                           ; And shift to pos 10:8
           mov   r7, a                       ; Save result of shift
           anl   a, #07h                     ; Select bits 0:2
           mov   r1, a
           mov   a, B                        ; Load PHY address
           anl   a, #1fh
           rl    a
           rl    a
           rl    a                           ; shift to 7:3
           orl   a, r1
           mov   r1, a

           mov   a, r7                       ; Restore result of shift
           anl   a, #0c0h                    ; Select bits 7:6
           mov   r0, a

           mov   a, #CSR_MII_ADDR
           acall ETH_WriteCSR
           
           ; Wait until MII is not busy
eth_rmii_busy2:
           mov   a, #CSR_MII_ADDR
           acall ETH_ReadCSR

           mov   a, r0
           jb    ACC.0, eth_rmii_busy2

           ; Read MII data register
           mov   a, #CSR_MII_DATA
           acall ETH_ReadCSR

           pop   EIE
           ret


;****************************************************************************
;*
;* Function Name: ETH_WriteMII
;*
;*   Description: Write MII register
;*
;*      Input(s): a -> register number, b -> PHY number, r1:r0 -> data
;*
;*    Outputs(s): N/A
;*
;****************************************************************************
ETH_WriteMII:
           push  EIE
           clr   EIE.5

           push  0                           ; Save r1 and r0
           push  1

           mov   r7, a                       ; Save register number
           ; Wait until MII is not busy
eth_wmii_busy:
           mov   a, #CSR_MII_ADDR
           acall ETH_ReadCSR

           mov   a, r0
           jb    ACC.0, eth_wmii_busy

           pop   1
           pop   0

           clr   a
           mov   r3, a                       ; Reserved - always clear
           mov   r2, a

           ; Write MII data register
           mov   a, #CSR_MII_DATA
           acall ETH_WriteCSR

           mov   a, r7                       ; Restore register number
           rr    a
           rr    a                           ; And shift to pos 0:2
           mov   r7, a                       ; Save result of shift
           anl   a, #07h                     ; Select bits 0:2
           mov   r1, a
           mov   a, B                        ; Load PHY address
           anl   a, #1fh
           rl    a
           rl    a
           rl    a                           ; shift to 7:3
           orl   a, r1
           mov   r1, a

           mov   a, r7                       ; Restore result of shift
           anl   a, #0c0h                    ; Select bits 7:6
           orl   a, #2                       ; Select write bit :1:
           mov   r0, a

           mov   a, #CSR_MII_ADDR
           acall ETH_WriteCSR
           
           pop   EIE
           ret


;****************************************************************************
;*
;* Function Name: Add_Dptr0_16
;*
;*   Description: Add the contents of 16 bit value in ba to dptr0.
;*
;*      Input(s): a    -> addend1 (low byte). 
;*                b    -> addend1 (high byte). 
;*                dptr0-> addend2.
;*
;*    Outputs(s): dptr0 = dptr0 + (ba). 
;*                
;****************************************************************************
Add_Dptr0_16:
          push  PSW
          push  ACC

          add   a, dpl
          mov   dpl, a
          mov   a, dph
          addc  a, B
          mov   dph, a
          jnc   exit
          inc   dpx
exit:
          pop   ACC
          pop   PSW
          ret

end