ask.vhd

VHDL语言编写的调制过程

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ask is
  port(clk,start,x:in std_logic;
            a:out std_logic;
            yy:out std_logic;
            y:out std_logic);
end ask;
architecture beha of ask is
 component modulation 
   port(clk,start,x: in std_logic;
        a:out std_logic;
        y:out std_logic);

 end component;
 component jietiao 
 port(clk      :in std_logic;         
     start    :in std_logic;        
     x      :in std_logic;          
     y      :out std_logic); 
 end component;
 signal y0: std_logic;

begin
 d1:modulation port map(clk=>clk,start=>start,x=>x,a=>a,y=>y0);
 d2:jietiao  port map(clk=>clk,start=>start,x=>y0,y=>y);
yy<=y0;
 
end beha;