modulation.vhd

VHDL语言编写的调制过程

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity modulation is
  port(clk,start,x:in std_logic;
          a:out std_logic;   
         y:out std_logic);
end modulation;
architecture beha of modulation is
  signal f:std_logic;
  signal count:std_logic_vector(1 downto 0);
   begin
  s0: process(clk)
     begin
      if clk'event and clk='1' then
        if start='0'then 
          count<="00";
        else  
          count<=count+'1';
       end if;
     end if;
 if count="10" then
        f<='1';
       elsif  count="11" then
        f<='1';
       else  f<='0';
      end if;

    end process s0;
   
     a<=f;
   y<=x and f;
   end beha;