jietiao.vhd

来自「VHDL语言编写的调制过程」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jietiao is
port(clk      :in std_logic;         
     start    :in std_logic;        
     x      :in std_logic;          
     y      :out std_logic);        
end jietiao;
architecture behav of jietiao is

signal q:integer range 0 to 32;        
signal xx:std_logic;               
begin
process(clk)
begin                      
    if clk'event and clk='1' then xx<=x;
         if start='1'then
             if   xx='1'  then 
                 if q=32 then q<=0;y<='0';xx<='0';
                    else q<=q+1;y<='1';xx<='1';
                  end if;
             else  y<='0';
            end if;
         end if;
     end if;  
end process ;
end behav;