demodulation.vhd

来自「VHDL语言编写的调制过程」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity demodulation is
port(clk      :in std_logic;         
     start    :in std_logic;         
     x      :in std_logic;      
     y      :out std_logic);       
end demodulation;
architecture beha of demodulation is
signal count1:integer range 0 to 31;        
signal xx:std_logic;                
signal count2:integer range 0 to 7;        
begin
s0:process(clk)                     
begin
if clk'event and clk='1' then xx<=x;  
   if start='0' then count1<=0;           
   elsif count1=31 then count1<=0;
   else count1<=count1+1;
   end if;
end if;
end process s0;
s1:process(xx,count1)                
begin 
if count1=31 then count2<=0;               
elsif count1=25 then             
   if  count2<=4 then y<='0';          
   else y<='1';
   end if;
elsif  xx'event and xx='1'then count2<=count2+1; 
end if;
end process s1;
end beha;