dff1.vhd

单片机和FPGA共同组成的系统

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DFF1 IS 
PORT (CLK,D:IN STD_LOGIC;
      Q: OUT STD_LOGIC );
END;
ARCHITECTURE BHV OF DFF1 IS
BEGIN
PROCESS (CLK) 
VARIABLE A,B: STD_LOGIC;
BEGIN
IF CLK'EVENT AND CLK='1' THEN 
A:=not D;
B:=A;
Q<=B;
END IF;
END PROCESS;
END;