test3.tan.qmsg

单片机和FPGA共同组成的系统

{ "Info" "ITDB_TH_RESULT" "DFF1:inst2\|Q EN DCCLK -0.979 ns register " "Info: th for register \"DFF1:inst2\|Q\" (data pin = \"EN\", clock pin = \"DCCLK\") is -0.979 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCCLK destination 6.829 ns + Longest register " "Info: + Longest clock path from clock \"DCCLK\" to destination register is 6.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DCCLK 1 CLK PIN_26 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_26; Fanout = 33; CLK Node = 'DCCLK'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DCCLK } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 120 -208 -40 136 "DCCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.649 ns) + CELL(0.711 ns) 6.829 ns DFF1:inst2\|Q 2 REG LC_X10_Y7_N2 64 " "Info: 2: + IC(4.649 ns) + CELL(0.711 ns) = 6.829 ns; Loc. = LC_X10_Y7_N2; Fanout = 64; REG Node = 'DFF1:inst2\|Q'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.360 ns" { DCCLK DFF1:inst2|Q } "NODE_NAME" } } { "DFF1.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/DFF1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.92 % ) " "Info: Total cell delay = 2.180 ns ( 31.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.649 ns ( 68.08 % ) " "Info: Total interconnect delay = 4.649 ns ( 68.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.829 ns" { DCCLK DFF1:inst2|Q } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.829 ns" { DCCLK DCCLK~out0 DFF1:inst2|Q } { 0.000ns 0.000ns 4.649ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "DFF1.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/DFF1.vhd" 5 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.823 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.823 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns EN 1 PIN PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'EN'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 136 -208 -40 152 "EN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.045 ns) + CELL(0.309 ns) 7.823 ns DFF1:inst2\|Q 2 REG LC_X10_Y7_N2 64 " "Info: 2: + IC(6.045 ns) + CELL(0.309 ns) = 7.823 ns; Loc. = LC_X10_Y7_N2; Fanout = 64; REG Node = 'DFF1:inst2\|Q'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.354 ns" { EN DFF1:inst2|Q } "NODE_NAME" } } { "DFF1.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/DFF1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 22.73 % ) " "Info: Total cell delay = 1.778 ns ( 22.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.045 ns ( 77.27 % ) " "Info: Total interconnect delay = 6.045 ns ( 77.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.823 ns" { EN DFF1:inst2|Q } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "7.823 ns" { EN EN~out0 DFF1:inst2|Q } { 0.000ns 0.000ns 6.045ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.829 ns" { DCCLK DFF1:inst2|Q } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.829 ns" { DCCLK DCCLK~out0 DFF1:inst2|Q } { 0.000ns 0.000ns 4.649ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.823 ns" { EN DFF1:inst2|Q } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "7.823 ns" { EN EN~out0 DFF1:inst2|Q } { 0.000ns 0.000ns 6.045ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 27 08:22:45 2008 " "Info: Processing ended: Fri Jun 27 08:22:45 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}