test3.tan.qmsg

单片机和FPGA共同组成的系统

{ "Info" "ITDB_TSU_RESULT" "DFF1:inst2\|Q EN DCCLK 1.031 ns register " "Info: tsu for register \"DFF1:inst2\|Q\" (data pin = \"EN\", clock pin = \"DCCLK\") is 1.031 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.823 ns + Longest pin register " "Info: + Longest pin to register delay is 7.823 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns EN 1 PIN PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'EN'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 136 -208 -40 152 "EN" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.045 ns) + CELL(0.309 ns) 7.823 ns DFF1:inst2\|Q 2 REG LC_X10_Y7_N2 64 " "Info: 2: + IC(6.045 ns) + CELL(0.309 ns) = 7.823 ns; Loc. = LC_X10_Y7_N2; Fanout = 64; REG Node = 'DFF1:inst2\|Q'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.354 ns" { EN DFF1:inst2|Q } "NODE_NAME" } } { "DFF1.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/DFF1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 22.73 % ) " "Info: Total cell delay = 1.778 ns ( 22.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.045 ns ( 77.27 % ) " "Info: Total interconnect delay = 6.045 ns ( 77.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.823 ns" { EN DFF1:inst2|Q } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "7.823 ns" { EN EN~out0 DFF1:inst2|Q } { 0.000ns 0.000ns 6.045ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "DFF1.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/DFF1.vhd" 5 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCCLK destination 6.829 ns - Shortest register " "Info: - Shortest clock path from clock \"DCCLK\" to destination register is 6.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DCCLK 1 CLK PIN_26 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_26; Fanout = 33; CLK Node = 'DCCLK'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DCCLK } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 120 -208 -40 136 "DCCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.649 ns) + CELL(0.711 ns) 6.829 ns DFF1:inst2\|Q 2 REG LC_X10_Y7_N2 64 " "Info: 2: + IC(4.649 ns) + CELL(0.711 ns) = 6.829 ns; Loc. = LC_X10_Y7_N2; Fanout = 64; REG Node = 'DFF1:inst2\|Q'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.360 ns" { DCCLK DFF1:inst2|Q } "NODE_NAME" } } { "DFF1.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/DFF1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.92 % ) " "Info: Total cell delay = 2.180 ns ( 31.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.649 ns ( 68.08 % ) " "Info: Total interconnect delay = 4.649 ns ( 68.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.829 ns" { DCCLK DFF1:inst2|Q } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.829 ns" { DCCLK DCCLK~out0 DFF1:inst2|Q } { 0.000ns 0.000ns 4.649ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.823 ns" { EN DFF1:inst2|Q } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "7.823 ns" { EN EN~out0 DFF1:inst2|Q } { 0.000ns 0.000ns 6.045ns } { 0.000ns 1.469ns 0.309ns } } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.829 ns" { DCCLK DFF1:inst2|Q } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.829 ns" { DCCLK DCCLK~out0 DFF1:inst2|Q } { 0.000ns 0.000ns 4.649ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "DCCLK DATAL\[1\] TF:inst5\|Q1\[17\] 17.381 ns register " "Info: tco from clock \"DCCLK\" to destination pin \"DATAL\[1\]\" through register \"TF:inst5\|Q1\[17\]\" is 17.381 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCCLK source 6.857 ns + Longest register " "Info: + Longest clock path from clock \"DCCLK\" to source register is 6.857 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DCCLK 1 CLK PIN_26 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_26; Fanout = 33; CLK Node = 'DCCLK'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DCCLK } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 120 -208 -40 136 "DCCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.677 ns) + CELL(0.711 ns) 6.857 ns TF:inst5\|Q1\[17\] 2 REG LC_X10_Y9_N1 4 " "Info: 2: + IC(4.677 ns) + CELL(0.711 ns) = 6.857 ns; Loc. = LC_X10_Y9_N1; Fanout = 4; REG Node = 'TF:inst5\|Q1\[17\]'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.388 ns" { DCCLK TF:inst5|Q1[17] } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.79 % ) " "Info: Total cell delay = 2.180 ns ( 31.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.677 ns ( 68.21 % ) " "Info: Total interconnect delay = 4.677 ns ( 68.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.857 ns" { DCCLK TF:inst5|Q1[17] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.857 ns" { DCCLK DCCLK~out0 TF:inst5|Q1[17] } { 0.000ns 0.000ns 4.677ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.300 ns + Longest register pin " "Info: + Longest register to pin delay is 10.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TF:inst5\|Q1\[17\] 1 REG LC_X10_Y9_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y9_N1; Fanout = 4; REG Node = 'TF:inst5\|Q1\[17\]'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TF:inst5|Q1[17] } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.703 ns) + CELL(0.590 ns) 2.293 ns SEND2:inst\|Mux2~37 2 COMB LC_X12_Y11_N4 1 " "Info: 2: + IC(1.703 ns) + CELL(0.590 ns) = 2.293 ns; Loc. = LC_X12_Y11_N4; Fanout = 1; COMB Node = 'SEND2:inst\|Mux2~37'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.293 ns" { TF:inst5|Q1[17] SEND2:inst|Mux2~37 } "NODE_NAME" } } { "SEND2.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/SEND2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.165 ns) + CELL(0.590 ns) 4.048 ns SEND2:inst\|Mux2~38 3 COMB LC_X10_Y11_N4 1 " "Info: 3: + IC(1.165 ns) + CELL(0.590 ns) = 4.048 ns; Loc. = LC_X10_Y11_N4; Fanout = 1; COMB Node = 'SEND2:inst\|Mux2~38'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.755 ns" { SEND2:inst|Mux2~37 SEND2:inst|Mux2~38 } "NODE_NAME" } } { "SEND2.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/SEND2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.192 ns) + CELL(0.442 ns) 5.682 ns SEND2:inst\|Mux2~41 4 COMB LC_X11_Y10_N3 1 " "Info: 4: + IC(1.192 ns) + CELL(0.442 ns) = 5.682 ns; Loc. = LC_X11_Y10_N3; Fanout = 1; COMB Node = 'SEND2:inst\|Mux2~41'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.634 ns" { SEND2:inst|Mux2~38 SEND2:inst|Mux2~41 } "NODE_NAME" } } { "SEND2.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/SEND2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.494 ns) + CELL(2.124 ns) 10.300 ns DATAL\[1\] 5 PIN PIN_6 0 " "Info: 5: + IC(2.494 ns) + CELL(2.124 ns) = 10.300 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'DATAL\[1\]'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.618 ns" { SEND2:inst|Mux2~41 DATAL[1] } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 152 792 968 168 "DATAL\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 36.37 % ) " "Info: Total cell delay = 3.746 ns ( 36.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.554 ns ( 63.63 % ) " "Info: Total interconnect delay = 6.554 ns ( 63.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.300 ns" { TF:inst5|Q1[17] SEND2:inst|Mux2~37 SEND2:inst|Mux2~38 SEND2:inst|Mux2~41 DATAL[1] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "10.300 ns" { TF:inst5|Q1[17] SEND2:inst|Mux2~37 SEND2:inst|Mux2~38 SEND2:inst|Mux2~41 DATAL[1] } { 0.000ns 1.703ns 1.165ns 1.192ns 2.494ns } { 0.000ns 0.590ns 0.590ns 0.442ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.857 ns" { DCCLK TF:inst5|Q1[17] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.857 ns" { DCCLK DCCLK~out0 TF:inst5|Q1[17] } { 0.000ns 0.000ns 4.677ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.300 ns" { TF:inst5|Q1[17] SEND2:inst|Mux2~37 SEND2:inst|Mux2~38 SEND2:inst|Mux2~41 DATAL[1] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "10.300 ns" { TF:inst5|Q1[17] SEND2:inst|Mux2~37 SEND2:inst|Mux2~38 SEND2:inst|Mux2~41 DATAL[1] } { 0.000ns 1.703ns 1.165ns 1.192ns 2.494ns } { 0.000ns 0.590ns 0.590ns 0.442ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SE\[1\] DATAL\[2\] 17.087 ns Longest " "Info: Longest tpd from source pin \"SE\[1\]\" to destination pin \"DATAL\[2\]\" is 17.087 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns SE\[1\] 1 PIN PIN_37 24 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_37; Fanout = 24; PIN Node = 'SE\[1\]'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SE[1] } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 312 -208 -40 328 "SE\[2..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.444 ns) + CELL(0.590 ns) 9.509 ns SEND2:inst\|Mux1~37 2 COMB LC_X10_Y8_N6 1 " "Info: 2: + IC(7.444 ns) + CELL(0.590 ns) = 9.509 ns; Loc. = LC_X10_Y8_N6; Fanout = 1; COMB Node = 'SEND2:inst\|Mux1~37'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.034 ns" { SE[1] SEND2:inst|Mux1~37 } "NODE_NAME" } } { "SEND2.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/SEND2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.222 ns) + CELL(0.114 ns) 10.845 ns SEND2:inst\|Mux1~38 3 COMB LC_X10_Y11_N3 1 " "Info: 3: + IC(1.222 ns) + CELL(0.114 ns) = 10.845 ns; Loc. = LC_X10_Y11_N3; Fanout = 1; COMB Node = 'SEND2:inst\|Mux1~38'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.336 ns" { SEND2:inst|Mux1~37 SEND2:inst|Mux1~38 } "NODE_NAME" } } { "SEND2.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/SEND2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(0.590 ns) 12.995 ns SEND2:inst\|Mux1~41 4 COMB LC_X9_Y10_N4 1 " "Info: 4: + IC(1.560 ns) + CELL(0.590 ns) = 12.995 ns; Loc. = LC_X9_Y10_N4; Fanout = 1; COMB Node = 'SEND2:inst\|Mux1~41'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.150 ns" { SEND2:inst|Mux1~38 SEND2:inst|Mux1~41 } "NODE_NAME" } } { "SEND2.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/SEND2.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.968 ns) + CELL(2.124 ns) 17.087 ns DATAL\[2\] 5 PIN PIN_7 0 " "Info: 5: + IC(1.968 ns) + CELL(2.124 ns) = 17.087 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'DATAL\[2\]'" {  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.092 ns" { SEND2:inst|Mux1~41 DATAL[2] } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 152 792 968 168 "DATAL\[3..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.893 ns ( 28.64 % ) " "Info: Total cell delay = 4.893 ns ( 28.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.194 ns ( 71.36 % ) " "Info: Total interconnect delay = 12.194 ns ( 71.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.087 ns" { SE[1] SEND2:inst|Mux1~37 SEND2:inst|Mux1~38 SEND2:inst|Mux1~41 DATAL[2] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "17.087 ns" { SE[1] SE[1]~out0 SEND2:inst|Mux1~37 SEND2:inst|Mux1~38 SEND2:inst|Mux1~41 DATAL[2] } { 0.000ns 0.000ns 7.444ns 1.222ns 1.560ns 1.968ns } { 0.000ns 1.475ns 0.590ns 0.114ns 0.590ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}