📄 test3.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "BZCLK " "Info: Assuming node \"BZCLK\" is an undefined clock" { } { { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 264 -208 -40 280 "BZCLK" "" } } } } { "c:/prosoft/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/prosoft/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "BZCLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "DCCLK " "Info: Assuming node \"DCCLK\" is an undefined clock" { } { { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 120 -208 -40 136 "DCCLK" "" } } } } { "c:/prosoft/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/prosoft/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DCCLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "BZCLK register register BZH:inst1\|Q1\[0\] BZH:inst1\|Q1\[31\] 275.03 MHz Internal " "Info: Clock \"BZCLK\" Internal fmax is restricted to 275.03 MHz between source register \"BZH:inst1\|Q1\[0\]\" and destination register \"BZH:inst1\|Q1\[31\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.284 ns + Longest register register " "Info: + Longest register to register delay is 3.284 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BZH:inst1\|Q1\[0\] 1 REG LC_X12_Y10_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y10_N1; Fanout = 6; REG Node = 'BZH:inst1\|Q1\[0\]'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BZH:inst1|Q1[0] } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.548 ns) + CELL(0.575 ns) 1.123 ns BZH:inst1\|Q1\[1\]~1937COUT1_1951 2 COMB LC_X12_Y10_N5 2 " "Info: 2: + IC(0.548 ns) + CELL(0.575 ns) = 1.123 ns; Loc. = LC_X12_Y10_N5; Fanout = 2; COMB Node = 'BZH:inst1\|Q1\[1\]~1937COUT1_1951'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.123 ns" { BZH:inst1|Q1[0] BZH:inst1|Q1[1]~1937COUT1_1951 } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.203 ns BZH:inst1\|Q1\[2\]~1929COUT1_1952 3 COMB LC_X12_Y10_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.203 ns; Loc. = LC_X12_Y10_N6; Fanout = 2; COMB Node = 'BZH:inst1\|Q1\[2\]~1929COUT1_1952'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { BZH:inst1|Q1[1]~1937COUT1_1951 BZH:inst1|Q1[2]~1929COUT1_1952 } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.283 ns BZH:inst1\|Q1\[3\]~1921COUT1_1953 4 COMB LC_X12_Y10_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.283 ns; Loc. = LC_X12_Y10_N7; Fanout = 2; COMB Node = 'BZH:inst1\|Q1\[3\]~1921COUT1_1953'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { BZH:inst1|Q1[2]~1929COUT1_1952 BZH:inst1|Q1[3]~1921COUT1_1953 } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.363 ns BZH:inst1\|Q1\[4\]~1948COUT1_1954 5 COMB LC_X12_Y10_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.363 ns; Loc. = LC_X12_Y10_N8; Fanout = 2; COMB Node = 'BZH:inst1\|Q1\[4\]~1948COUT1_1954'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { BZH:inst1|Q1[3]~1921COUT1_1953 BZH:inst1|Q1[4]~1948COUT1_1954 } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.621 ns BZH:inst1\|Q1\[5\]~1941 6 COMB LC_X12_Y10_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.621 ns; Loc. = LC_X12_Y10_N9; Fanout = 6; COMB Node = 'BZH:inst1\|Q1\[5\]~1941'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { BZH:inst1|Q1[4]~1948COUT1_1954 BZH:inst1|Q1[5]~1941 } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.757 ns BZH:inst1\|Q1\[10\]~1926 7 COMB LC_X12_Y9_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.757 ns; Loc. = LC_X12_Y9_N4; Fanout = 6; COMB Node = 'BZH:inst1\|Q1\[10\]~1926'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { BZH:inst1|Q1[5]~1941 BZH:inst1|Q1[10]~1926 } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.965 ns BZH:inst1\|Q1\[15\]~1923 8 COMB LC_X12_Y9_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 1.965 ns; Loc. = LC_X12_Y9_N9; Fanout = 6; COMB Node = 'BZH:inst1\|Q1\[15\]~1923'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { BZH:inst1|Q1[10]~1926 BZH:inst1|Q1[15]~1923 } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.101 ns BZH:inst1\|Q1\[20\]~1945 9 COMB LC_X12_Y8_N4 6 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 2.101 ns; Loc. = LC_X12_Y8_N4; Fanout = 6; COMB Node = 'BZH:inst1\|Q1\[20\]~1945'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { BZH:inst1|Q1[15]~1923 BZH:inst1|Q1[20]~1945 } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.309 ns BZH:inst1\|Q1\[25\]~1936 10 COMB LC_X12_Y8_N9 6 " "Info: 10: + IC(0.000 ns) + CELL(0.208 ns) = 2.309 ns; Loc. = LC_X12_Y8_N9; Fanout = 6; COMB Node = 'BZH:inst1\|Q1\[25\]~1936'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { BZH:inst1|Q1[20]~1945 BZH:inst1|Q1[25]~1936 } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.445 ns BZH:inst1\|Q1\[30\]~1932 11 COMB LC_X12_Y7_N4 1 " "Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 2.445 ns; Loc. = LC_X12_Y7_N4; Fanout = 1; COMB Node = 'BZH:inst1\|Q1\[30\]~1932'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { BZH:inst1|Q1[25]~1936 BZH:inst1|Q1[30]~1932 } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 3.284 ns BZH:inst1\|Q1\[31\] 12 REG LC_X12_Y7_N5 3 " "Info: 12: + IC(0.000 ns) + CELL(0.839 ns) = 3.284 ns; Loc. = LC_X12_Y7_N5; Fanout = 3; REG Node = 'BZH:inst1\|Q1\[31\]'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { BZH:inst1|Q1[30]~1932 BZH:inst1|Q1[31] } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 83.31 % ) " "Info: Total cell delay = 2.736 ns ( 83.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.548 ns ( 16.69 % ) " "Info: Total interconnect delay = 0.548 ns ( 16.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.284 ns" { BZH:inst1|Q1[0] BZH:inst1|Q1[1]~1937COUT1_1951 BZH:inst1|Q1[2]~1929COUT1_1952 BZH:inst1|Q1[3]~1921COUT1_1953 BZH:inst1|Q1[4]~1948COUT1_1954 BZH:inst1|Q1[5]~1941 BZH:inst1|Q1[10]~1926 BZH:inst1|Q1[15]~1923 BZH:inst1|Q1[20]~1945 BZH:inst1|Q1[25]~1936 BZH:inst1|Q1[30]~1932 BZH:inst1|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "3.284 ns" { BZH:inst1|Q1[0] BZH:inst1|Q1[1]~1937COUT1_1951 BZH:inst1|Q1[2]~1929COUT1_1952 BZH:inst1|Q1[3]~1921COUT1_1953 BZH:inst1|Q1[4]~1948COUT1_1954 BZH:inst1|Q1[5]~1941 BZH:inst1|Q1[10]~1926 BZH:inst1|Q1[15]~1923 BZH:inst1|Q1[20]~1945 BZH:inst1|Q1[25]~1936 BZH:inst1|Q1[30]~1932 BZH:inst1|Q1[31] } { 0.000ns 0.548ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.028 ns - Smallest " "Info: - Smallest clock skew is -0.028 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BZCLK destination 2.740 ns + Shortest register " "Info: + Shortest clock path from clock \"BZCLK\" to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns BZCLK 1 CLK PIN_16 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 32; CLK Node = 'BZCLK'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BZCLK } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 264 -208 -40 280 "BZCLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns BZH:inst1\|Q1\[31\] 2 REG LC_X12_Y7_N5 3 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X12_Y7_N5; Fanout = 3; REG Node = 'BZH:inst1\|Q1\[31\]'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.271 ns" { BZCLK BZH:inst1|Q1[31] } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { BZCLK BZH:inst1|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { BZCLK BZCLK~out0 BZH:inst1|Q1[31] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "BZCLK source 2.768 ns - Longest register " "Info: - Longest clock path from clock \"BZCLK\" to source register is 2.768 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns BZCLK 1 CLK PIN_16 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 32; CLK Node = 'BZCLK'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BZCLK } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 264 -208 -40 280 "BZCLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.711 ns) 2.768 ns BZH:inst1\|Q1\[0\] 2 REG LC_X12_Y10_N1 6 " "Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X12_Y10_N1; Fanout = 6; REG Node = 'BZH:inst1\|Q1\[0\]'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.299 ns" { BZCLK BZH:inst1|Q1[0] } "NODE_NAME" } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.76 % ) " "Info: Total cell delay = 2.180 ns ( 78.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.588 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.588 ns ( 21.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { BZCLK BZH:inst1|Q1[0] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { BZCLK BZCLK~out0 BZH:inst1|Q1[0] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { BZCLK BZH:inst1|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { BZCLK BZCLK~out0 BZH:inst1|Q1[31] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { BZCLK BZH:inst1|Q1[0] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { BZCLK BZCLK~out0 BZH:inst1|Q1[0] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.284 ns" { BZH:inst1|Q1[0] BZH:inst1|Q1[1]~1937COUT1_1951 BZH:inst1|Q1[2]~1929COUT1_1952 BZH:inst1|Q1[3]~1921COUT1_1953 BZH:inst1|Q1[4]~1948COUT1_1954 BZH:inst1|Q1[5]~1941 BZH:inst1|Q1[10]~1926 BZH:inst1|Q1[15]~1923 BZH:inst1|Q1[20]~1945 BZH:inst1|Q1[25]~1936 BZH:inst1|Q1[30]~1932 BZH:inst1|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "3.284 ns" { BZH:inst1|Q1[0] BZH:inst1|Q1[1]~1937COUT1_1951 BZH:inst1|Q1[2]~1929COUT1_1952 BZH:inst1|Q1[3]~1921COUT1_1953 BZH:inst1|Q1[4]~1948COUT1_1954 BZH:inst1|Q1[5]~1941 BZH:inst1|Q1[10]~1926 BZH:inst1|Q1[15]~1923 BZH:inst1|Q1[20]~1945 BZH:inst1|Q1[25]~1936 BZH:inst1|Q1[30]~1932 BZH:inst1|Q1[31] } { 0.000ns 0.548ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { BZCLK BZH:inst1|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { BZCLK BZCLK~out0 BZH:inst1|Q1[31] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.768 ns" { BZCLK BZH:inst1|Q1[0] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "2.768 ns" { BZCLK BZCLK~out0 BZH:inst1|Q1[0] } { 0.000ns 0.000ns 0.588ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BZH:inst1|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { BZH:inst1|Q1[31] } { } { } } } { "BZH.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/BZH.vhd" 13 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "DCCLK register register TF:inst5\|Q1\[0\] TF:inst5\|Q1\[31\] 275.03 MHz Internal " "Info: Clock \"DCCLK\" Internal fmax is restricted to 275.03 MHz between source register \"TF:inst5\|Q1\[0\]\" and destination register \"TF:inst5\|Q1\[31\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.287 ns + Longest register register " "Info: + Longest register to register delay is 3.287 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TF:inst5\|Q1\[0\] 1 REG LC_X10_Y11_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y11_N2; Fanout = 5; REG Node = 'TF:inst5\|Q1\[0\]'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TF:inst5|Q1[0] } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.551 ns) + CELL(0.575 ns) 1.126 ns TF:inst5\|Q1\[1\]~177COUT1_191 2 COMB LC_X10_Y11_N5 2 " "Info: 2: + IC(0.551 ns) + CELL(0.575 ns) = 1.126 ns; Loc. = LC_X10_Y11_N5; Fanout = 2; COMB Node = 'TF:inst5\|Q1\[1\]~177COUT1_191'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.126 ns" { TF:inst5|Q1[0] TF:inst5|Q1[1]~177COUT1_191 } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.206 ns TF:inst5\|Q1\[2\]~169COUT1_192 3 COMB LC_X10_Y11_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.206 ns; Loc. = LC_X10_Y11_N6; Fanout = 2; COMB Node = 'TF:inst5\|Q1\[2\]~169COUT1_192'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { TF:inst5|Q1[1]~177COUT1_191 TF:inst5|Q1[2]~169COUT1_192 } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.286 ns TF:inst5\|Q1\[3\]~161COUT1_193 4 COMB LC_X10_Y11_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.286 ns; Loc. = LC_X10_Y11_N7; Fanout = 2; COMB Node = 'TF:inst5\|Q1\[3\]~161COUT1_193'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { TF:inst5|Q1[2]~169COUT1_192 TF:inst5|Q1[3]~161COUT1_193 } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.366 ns TF:inst5\|Q1\[4\]~188COUT1_194 5 COMB LC_X10_Y11_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.366 ns; Loc. = LC_X10_Y11_N8; Fanout = 2; COMB Node = 'TF:inst5\|Q1\[4\]~188COUT1_194'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { TF:inst5|Q1[3]~161COUT1_193 TF:inst5|Q1[4]~188COUT1_194 } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.624 ns TF:inst5\|Q1\[5\]~181 6 COMB LC_X10_Y11_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.624 ns; Loc. = LC_X10_Y11_N9; Fanout = 6; COMB Node = 'TF:inst5\|Q1\[5\]~181'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { TF:inst5|Q1[4]~188COUT1_194 TF:inst5|Q1[5]~181 } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.760 ns TF:inst5\|Q1\[10\]~166 7 COMB LC_X10_Y10_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.760 ns; Loc. = LC_X10_Y10_N4; Fanout = 6; COMB Node = 'TF:inst5\|Q1\[10\]~166'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { TF:inst5|Q1[5]~181 TF:inst5|Q1[10]~166 } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.968 ns TF:inst5\|Q1\[15\]~163 8 COMB LC_X10_Y10_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 1.968 ns; Loc. = LC_X10_Y10_N9; Fanout = 6; COMB Node = 'TF:inst5\|Q1\[15\]~163'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { TF:inst5|Q1[10]~166 TF:inst5|Q1[15]~163 } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.104 ns TF:inst5\|Q1\[20\]~185 9 COMB LC_X10_Y9_N4 6 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 2.104 ns; Loc. = LC_X10_Y9_N4; Fanout = 6; COMB Node = 'TF:inst5\|Q1\[20\]~185'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { TF:inst5|Q1[15]~163 TF:inst5|Q1[20]~185 } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.312 ns TF:inst5\|Q1\[25\]~176 10 COMB LC_X10_Y9_N9 6 " "Info: 10: + IC(0.000 ns) + CELL(0.208 ns) = 2.312 ns; Loc. = LC_X10_Y9_N9; Fanout = 6; COMB Node = 'TF:inst5\|Q1\[25\]~176'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { TF:inst5|Q1[20]~185 TF:inst5|Q1[25]~176 } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.448 ns TF:inst5\|Q1\[30\]~172 11 COMB LC_X10_Y8_N4 1 " "Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 2.448 ns; Loc. = LC_X10_Y8_N4; Fanout = 1; COMB Node = 'TF:inst5\|Q1\[30\]~172'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { TF:inst5|Q1[25]~176 TF:inst5|Q1[30]~172 } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 3.287 ns TF:inst5\|Q1\[31\] 12 REG LC_X10_Y8_N5 2 " "Info: 12: + IC(0.000 ns) + CELL(0.839 ns) = 3.287 ns; Loc. = LC_X10_Y8_N5; Fanout = 2; REG Node = 'TF:inst5\|Q1\[31\]'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { TF:inst5|Q1[30]~172 TF:inst5|Q1[31] } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 83.24 % ) " "Info: Total cell delay = 2.736 ns ( 83.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.551 ns ( 16.76 % ) " "Info: Total interconnect delay = 0.551 ns ( 16.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.287 ns" { TF:inst5|Q1[0] TF:inst5|Q1[1]~177COUT1_191 TF:inst5|Q1[2]~169COUT1_192 TF:inst5|Q1[3]~161COUT1_193 TF:inst5|Q1[4]~188COUT1_194 TF:inst5|Q1[5]~181 TF:inst5|Q1[10]~166 TF:inst5|Q1[15]~163 TF:inst5|Q1[20]~185 TF:inst5|Q1[25]~176 TF:inst5|Q1[30]~172 TF:inst5|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "3.287 ns" { TF:inst5|Q1[0] TF:inst5|Q1[1]~177COUT1_191 TF:inst5|Q1[2]~169COUT1_192 TF:inst5|Q1[3]~161COUT1_193 TF:inst5|Q1[4]~188COUT1_194 TF:inst5|Q1[5]~181 TF:inst5|Q1[10]~166 TF:inst5|Q1[15]~163 TF:inst5|Q1[20]~185 TF:inst5|Q1[25]~176 TF:inst5|Q1[30]~172 TF:inst5|Q1[31] } { 0.000ns 0.551ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.028 ns - Smallest " "Info: - Smallest clock skew is -0.028 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCCLK destination 6.829 ns + Shortest register " "Info: + Shortest clock path from clock \"DCCLK\" to destination register is 6.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DCCLK 1 CLK PIN_26 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_26; Fanout = 33; CLK Node = 'DCCLK'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DCCLK } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 120 -208 -40 136 "DCCLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.649 ns) + CELL(0.711 ns) 6.829 ns TF:inst5\|Q1\[31\] 2 REG LC_X10_Y8_N5 2 " "Info: 2: + IC(4.649 ns) + CELL(0.711 ns) = 6.829 ns; Loc. = LC_X10_Y8_N5; Fanout = 2; REG Node = 'TF:inst5\|Q1\[31\]'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.360 ns" { DCCLK TF:inst5|Q1[31] } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.92 % ) " "Info: Total cell delay = 2.180 ns ( 31.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.649 ns ( 68.08 % ) " "Info: Total interconnect delay = 4.649 ns ( 68.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.829 ns" { DCCLK TF:inst5|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.829 ns" { DCCLK DCCLK~out0 TF:inst5|Q1[31] } { 0.000ns 0.000ns 4.649ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCCLK source 6.857 ns - Longest register " "Info: - Longest clock path from clock \"DCCLK\" to source register is 6.857 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DCCLK 1 CLK PIN_26 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_26; Fanout = 33; CLK Node = 'DCCLK'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DCCLK } "NODE_NAME" } } { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 120 -208 -40 136 "DCCLK" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.677 ns) + CELL(0.711 ns) 6.857 ns TF:inst5\|Q1\[0\] 2 REG LC_X10_Y11_N2 5 " "Info: 2: + IC(4.677 ns) + CELL(0.711 ns) = 6.857 ns; Loc. = LC_X10_Y11_N2; Fanout = 5; REG Node = 'TF:inst5\|Q1\[0\]'" { } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.388 ns" { DCCLK TF:inst5|Q1[0] } "NODE_NAME" } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.79 % ) " "Info: Total cell delay = 2.180 ns ( 31.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.677 ns ( 68.21 % ) " "Info: Total interconnect delay = 4.677 ns ( 68.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.857 ns" { DCCLK TF:inst5|Q1[0] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.857 ns" { DCCLK DCCLK~out0 TF:inst5|Q1[0] } { 0.000ns 0.000ns 4.677ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.829 ns" { DCCLK TF:inst5|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.829 ns" { DCCLK DCCLK~out0 TF:inst5|Q1[31] } { 0.000ns 0.000ns 4.649ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.857 ns" { DCCLK TF:inst5|Q1[0] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.857 ns" { DCCLK DCCLK~out0 TF:inst5|Q1[0] } { 0.000ns 0.000ns 4.677ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.287 ns" { TF:inst5|Q1[0] TF:inst5|Q1[1]~177COUT1_191 TF:inst5|Q1[2]~169COUT1_192 TF:inst5|Q1[3]~161COUT1_193 TF:inst5|Q1[4]~188COUT1_194 TF:inst5|Q1[5]~181 TF:inst5|Q1[10]~166 TF:inst5|Q1[15]~163 TF:inst5|Q1[20]~185 TF:inst5|Q1[25]~176 TF:inst5|Q1[30]~172 TF:inst5|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "3.287 ns" { TF:inst5|Q1[0] TF:inst5|Q1[1]~177COUT1_191 TF:inst5|Q1[2]~169COUT1_192 TF:inst5|Q1[3]~161COUT1_193 TF:inst5|Q1[4]~188COUT1_194 TF:inst5|Q1[5]~181 TF:inst5|Q1[10]~166 TF:inst5|Q1[15]~163 TF:inst5|Q1[20]~185 TF:inst5|Q1[25]~176 TF:inst5|Q1[30]~172 TF:inst5|Q1[31] } { 0.000ns 0.551ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.829 ns" { DCCLK TF:inst5|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.829 ns" { DCCLK DCCLK~out0 TF:inst5|Q1[31] } { 0.000ns 0.000ns 4.649ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.857 ns" { DCCLK TF:inst5|Q1[0] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "6.857 ns" { DCCLK DCCLK~out0 TF:inst5|Q1[0] } { 0.000ns 0.000ns 4.677ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0} } { { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TF:inst5|Q1[31] } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/prosoft/altera/quartus60/win/Technology_Viewer.qrui" "" { TF:inst5|Q1[31] } { } { } } } { "TF.vhd" "" { Text "C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd" 13 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
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