test3.fit.qmsg

单片机和FPGA共同组成的系统

{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "BZCLK Global clock in PIN 16 " "Info: Automatically promoted signal \"BZCLK\" to use Global clock in PIN 16" {  } { { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 264 -208 -40 280 "BZCLK" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "DCCLK Global clock " "Info: Automatically promoted signal \"DCCLK\" to use Global clock" {  } { { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 120 -208 -40 136 "DCCLK" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "DCCLK " "Info: Pin \"DCCLK\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 120 -208 -40 136 "DCCLK" "" } } } } { "c:/prosoft/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/prosoft/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DCCLK" } } } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DCCLK } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DCCLK } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RST Global clock " "Info: Automatically promoted signal \"RST\" to use Global clock" {  } { { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 280 -208 -40 296 "RST" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "RST " "Info: Pin \"RST\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "test3.bdf" "" { Schematic "C:/Documents and Settings/stu02/桌面/PJu/test3/test3.bdf" { { 280 -208 -40 296 "RST" "" } } } } { "c:/prosoft/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/prosoft/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "RST" } } } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RST } "NODE_NAME" } } { "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/prosoft/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RST } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}