test3.tan.summary

单片机和FPGA共同组成的系统

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.031 ns
From           : EN
To             : DFF1:inst2|Q
From Clock     : --
To Clock       : DCCLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.381 ns
From           : TF:inst5|Q1[17]
To             : DATAL[1]
From Clock     : DCCLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 17.087 ns
From           : SE[1]
To             : DATAL[2]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.979 ns
From           : EN
To             : DFF1:inst2|Q
From Clock     : --
To Clock       : DCCLK
Failed Paths   : 0

Type           : Clock Setup: 'DCCLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : TF:inst5|Q1[0]
To             : TF:inst5|Q1[31]
From Clock     : DCCLK
To Clock       : DCCLK
Failed Paths   : 0

Type           : Clock Setup: 'BZCLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : BZH:inst1|Q1[0]
To             : BZH:inst1|Q1[31]
From Clock     : BZCLK
To Clock       : BZCLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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