send3.vhd

单片机和FPGA共同组成的系统

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SEND3 IS
PORT (
      Q1,Q2:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
      SE:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      DATA1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;

ARCHITECTURE BHV OF SEND3 IS
BEGIN
PROCESS(SE,Q1,Q2)
VARIABLE I:STD_LOGIC;
BEGIN
CASE SE IS
WHEN  "0000" =>DATA1<=Q1(3  DOWNTO 0 );
WHEN  "0001" =>DATA1<=Q1(7  DOWNTO 4 );
WHEN  "0010" =>DATA1<=Q1(11 DOWNTO 8 );
WHEN  "0011" =>DATA1<=Q1(15 DOWNTO 12);
WHEN  "0100" =>DATA1<=Q1(19 DOWNTO 16);
WHEN  "0101" =>DATA1<=Q1(23 DOWNTO 20);
WHEN  "0110" =>DATA1<=Q1(27 DOWNTO 24);
WHEN  "0111" =>DATA1<=Q1(31 DOWNTO 28);
WHEN  "1000" =>DATA1<=Q2(3  DOWNTO 0 );
WHEN  "1001" =>DATA1<=Q2(7  DOWNTO 4 );
WHEN  "1010" =>DATA1<=Q2(11 DOWNTO 8 );
WHEN  "1011" =>DATA1<=Q2(15 DOWNTO 12);
WHEN  "1100" =>DATA1<=Q2(19 DOWNTO 16);
WHEN  "1101" =>DATA1<=Q2(23 DOWNTO 20);
WHEN  "1110" =>DATA1<=Q2(27 DOWNTO 24);
WHEN  "1111" =>DATA1<=Q2(31 DOWNTO 28);
END CASE;
END PROCESS;
END BHV;