test3.map.rpt

单片机和FPGA共同组成的系统

; TF.vhd                           ; yes             ; User VHDL File                     ; C:/Documents and Settings/stu02/桌面/PJu/test3/TF.vhd    ;
; SEND2.vhd                        ; yes             ; User VHDL File                     ; C:/Documents and Settings/stu02/桌面/PJu/test3/SEND2.vhd ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------+


+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                ;
+---------------------------------------------+--------------+
; Resource                                    ; Usage        ;
+---------------------------------------------+--------------+
; Total logic elements                        ; 105          ;
;     -- Combinational with no register       ; 40           ;
;     -- Register only                        ; 0            ;
;     -- Combinational with a register        ; 65           ;
;                                             ;              ;
; Logic element usage by number of LUT inputs ;              ;
;     -- 4 input functions                    ; 32           ;
;     -- 3 input functions                    ; 8            ;
;     -- 2 input functions                    ; 62           ;
;     -- 1 input functions                    ; 3            ;
;     -- 0 input functions                    ; 0            ;
;         -- Combinational cells for routing  ; 0            ;
;                                             ;              ;
; Logic elements by mode                      ;              ;
;     -- normal mode                          ; 45           ;
;     -- arithmetic mode                      ; 60           ;
;     -- qfbk mode                            ; 0            ;
;     -- register cascade mode                ; 0            ;
;     -- synchronous clear/load mode          ; 0            ;
;     -- asynchronous clear/load mode         ; 64           ;
;                                             ;              ;
; Total registers                             ; 65           ;
; Total logic cells in carry chains           ; 62           ;
; I/O pins                                    ; 47           ;
; Maximum fan-out node                        ; DFF1:inst2|Q ;
; Maximum fan-out                             ; 64           ;
; Total fan-out                               ; 512          ;
; Average fan-out                             ; 3.37         ;
+---------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |test3                     ; 105 (0)     ; 65           ; 0           ; 0    ; 47   ; 0            ; 40 (0)       ; 0 (0)             ; 65 (0)           ; 62 (0)          ; 0 (0)      ; |test3              ;
;    |BZH:inst1|             ; 32 (32)     ; 32           ; 0           ; 0    ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 31 (31)         ; 0 (0)      ; |test3|BZH:inst1    ;
;    |DFF1:inst2|            ; 1 (1)       ; 1            ; 0           ; 0    ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 1 (1)            ; 0 (0)           ; 0 (0)      ; |test3|DFF1:inst2   ;
;    |SEND2:inst|            ; 20 (20)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 20 (20)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |test3|SEND2:inst   ;
;    |SEND:inst4|            ; 20 (20)     ; 0            ; 0           ; 0    ; 0    ; 0            ; 20 (20)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |test3|SEND:inst4   ;
;    |TF:inst5|              ; 32 (32)     ; 32           ; 0           ; 0    ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 32 (32)          ; 31 (31)         ; 0 (0)      ; |test3|TF:inst5     ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 65    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 64    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 64    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 8:1                ; 8 bits    ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; No         ; |test3|SEND:inst4|Mux0     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Jun 27 08:22:26 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test3 -c test3
Info: Found 2 design units, including 1 entities, in source file BZH.vhd
    Info: Found design unit 1: BZH-BHV
    Info: Found entity 1: BZH
Info: Found 2 design units, including 1 entities, in source file DFF1.vhd
    Info: Found design unit 1: DFF1-BHV
    Info: Found entity 1: DFF1
Info: Found 2 design units, including 1 entities, in source file SEND.vhd
    Info: Found design unit 1: SEND-BHV
    Info: Found entity 1: SEND
Info: Found 1 design units, including 1 entities, in source file test3.bdf
    Info: Found entity 1: test3
Info: Found 2 design units, including 1 entities, in source file TF.vhd
    Info: Found design unit 1: TF-BHV
    Info: Found entity 1: TF
Info: Found 2 design units, including 1 entities, in source file SEND2.vhd
    Info: Found design unit 1: SEND2-BHV
    Info: Found entity 1: SEND2
Info: Found 2 design units, including 1 entities, in source file send3.vhd
    Info: Found design unit 1: SEND3-BHV
    Info: Found entity 1: SEND3
Info: Elaborating entity "test3" for the top level hierarchy
Info: Elaborating entity "SEND" for hierarchy "SEND:inst4"
Info: Elaborating entity "BZH" for hierarchy "BZH:inst1"
Info: Elaborating entity "DFF1" for hierarchy "DFF1:inst2"
Info: Elaborating entity "SEND2" for hierarchy "SEND2:inst"
Info: Elaborating entity "TF" for hierarchy "TF:inst5"
Info: Implemented 152 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 40 output pins
    Info: Implemented 105 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Jun 27 08:22:28 2008
    Info: Elapsed time: 00:00:02