send.vhd

来自「单片机和FPGA共同组成的系统」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SEND IS
PORT (
      Q:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
      SE:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
      DATA1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;

ARCHITECTURE BHV OF SEND IS
BEGIN
PROCESS(SE,Q)
VARIABLE I:STD_LOGIC;
BEGIN
CASE SE IS
WHEN  "000" =>DATA1<=Q(31  DOWNTO 28 );
WHEN  "001" =>DATA1<=Q(27  DOWNTO 24 );
WHEN  "010" =>DATA1<=Q(23 DOWNTO 20 );
WHEN  "011" =>DATA1<=Q(19 DOWNTO 16);
WHEN  "100" =>DATA1<=Q(15 DOWNTO 12);
WHEN  "101" =>DATA1<=Q(11 DOWNTO 8);
WHEN  "110" =>DATA1<=Q(7 DOWNTO 4);
WHEN  "111" =>DATA1<=Q(3 DOWNTO 0);
END CASE;
END PROCESS;
END BHV;