📄 prev_cmp_counter60.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register q\[2\]~reg0 q\[0\]~reg0 500.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 500.0 MHz between source register \"q\[2\]~reg0\" and destination register \"q\[0\]~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.430 ns + Longest register register " "Info: + Longest register to register delay is 1.430 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[2\]~reg0 1 REG LCFF_X30_Y3_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y3_N5; Fanout = 4; REG Node = 'q\[2\]~reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q[2]~reg0 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.345 ns) + CELL(0.228 ns) 0.573 ns Equal0~27 2 COMB LCCOMB_X30_Y3_N20 1 " "Info: 2: + IC(0.345 ns) + CELL(0.228 ns) = 0.573 ns; Loc. = LCCOMB_X30_Y3_N20; Fanout = 1; COMB Node = 'Equal0~27'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.573 ns" { q[2]~reg0 Equal0~27 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.194 ns) + CELL(0.053 ns) 0.820 ns q\[0\]~62 3 COMB LCCOMB_X30_Y3_N22 6 " "Info: 3: + IC(0.194 ns) + CELL(0.053 ns) = 0.820 ns; Loc. = LCCOMB_X30_Y3_N22; Fanout = 6; COMB Node = 'q\[0\]~62'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.247 ns" { Equal0~27 q[0]~62 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.213 ns) + CELL(0.397 ns) 1.430 ns q\[0\]~reg0 4 REG LCFF_X30_Y3_N1 4 " "Info: 4: + IC(0.213 ns) + CELL(0.397 ns) = 1.430 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.610 ns" { q[0]~62 q[0]~reg0 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.678 ns ( 47.41 % ) " "Info: Total cell delay = 0.678 ns ( 47.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.752 ns ( 52.59 % ) " "Info: Total interconnect delay = 0.752 ns ( 52.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.430 ns" { q[2]~reg0 Equal0~27 q[0]~62 q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.430 ns" { q[2]~reg0 {} Equal0~27 {} q[0]~62 {} q[0]~reg0 {} } { 0.000ns 0.345ns 0.194ns 0.213ns } { 0.000ns 0.228ns 0.053ns 0.397ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.484 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.618 ns) 2.484 ns q\[0\]~reg0 3 REG LCFF_X30_Y3_N1 4 " "Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.287 ns" { clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.26 % ) " "Info: Total cell delay = 1.472 ns ( 59.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.012 ns ( 40.74 % ) " "Info: Total interconnect delay = 1.012 ns ( 40.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.484 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.618 ns) 2.484 ns q\[2\]~reg0 3 REG LCFF_X30_Y3_N5 4 " "Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X30_Y3_N5; Fanout = 4; REG Node = 'q\[2\]~reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.287 ns" { clk~clkctrl q[2]~reg0 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.26 % ) " "Info: Total cell delay = 1.472 ns ( 59.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.012 ns ( 40.74 % ) " "Info: Total interconnect delay = 1.012 ns ( 40.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[2]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[2]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.430 ns" { q[2]~reg0 Equal0~27 q[0]~62 q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.430 ns" { q[2]~reg0 {} Equal0~27 {} q[0]~62 {} q[0]~reg0 {} } { 0.000ns 0.345ns 0.194ns 0.213ns } { 0.000ns 0.228ns 0.053ns 0.397ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[2]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { q[0]~reg0 {} } { } { } "" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "q\[0\]~reg0 clr clk 3.177 ns register " "Info: tsu for register \"q\[0\]~reg0\" (data pin = \"clr\", clock pin = \"clk\") is 3.177 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.571 ns + Longest pin register " "Info: + Longest pin to register delay is 5.571 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.817 ns) 0.817 ns clr 1 PIN PIN_U10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.817 ns) = 0.817 ns; Loc. = PIN_U10; Fanout = 1; PIN Node = 'clr'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.798 ns) + CELL(0.346 ns) 4.961 ns q\[0\]~62 2 COMB LCCOMB_X30_Y3_N22 6 " "Info: 2: + IC(3.798 ns) + CELL(0.346 ns) = 4.961 ns; Loc. = LCCOMB_X30_Y3_N22; Fanout = 6; COMB Node = 'q\[0\]~62'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.144 ns" { clr q[0]~62 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.213 ns) + CELL(0.397 ns) 5.571 ns q\[0\]~reg0 3 REG LCFF_X30_Y3_N1 4 " "Info: 3: + IC(0.213 ns) + CELL(0.397 ns) = 5.571 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.610 ns" { q[0]~62 q[0]~reg0 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.560 ns ( 28.00 % ) " "Info: Total cell delay = 1.560 ns ( 28.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.011 ns ( 72.00 % ) " "Info: Total interconnect delay = 4.011 ns ( 72.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.571 ns" { clr q[0]~62 q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.571 ns" { clr {} clr~combout {} q[0]~62 {} q[0]~reg0 {} } { 0.000ns 0.000ns 3.798ns 0.213ns } { 0.000ns 0.817ns 0.346ns 0.397ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.484 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.618 ns) 2.484 ns q\[0\]~reg0 3 REG LCFF_X30_Y3_N1 4 " "Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.287 ns" { clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.26 % ) " "Info: Total cell delay = 1.472 ns ( 59.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.012 ns ( 40.74 % ) " "Info: Total interconnect delay = 1.012 ns ( 40.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.571 ns" { clr q[0]~62 q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.571 ns" { clr {} clr~combout {} q[0]~62 {} q[0]~reg0 {} } { 0.000ns 0.000ns 3.798ns 0.213ns } { 0.000ns 0.817ns 0.346ns 0.397ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[2\] q\[2\]~reg0 5.609 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[2\]\" through register \"q\[2\]~reg0\" is 5.609 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.484 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.618 ns) 2.484 ns q\[2\]~reg0 3 REG LCFF_X30_Y3_N5 4 " "Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X30_Y3_N5; Fanout = 4; REG Node = 'q\[2\]~reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.287 ns" { clk~clkctrl q[2]~reg0 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.26 % ) " "Info: Total cell delay = 1.472 ns ( 59.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.012 ns ( 40.74 % ) " "Info: Total interconnect delay = 1.012 ns ( 40.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[2]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.031 ns + Longest register pin " "Info: + Longest register to pin delay is 3.031 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[2\]~reg0 1 REG LCFF_X30_Y3_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y3_N5; Fanout = 4; REG Node = 'q\[2\]~reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q[2]~reg0 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.877 ns) + CELL(2.154 ns) 3.031 ns q\[2\] 2 PIN PIN_V1 0 " "Info: 2: + IC(0.877 ns) + CELL(2.154 ns) = 3.031 ns; Loc. = PIN_V1; Fanout = 0; PIN Node = 'q\[2\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.031 ns" { q[2]~reg0 q[2] } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.154 ns ( 71.07 % ) " "Info: Total cell delay = 2.154 ns ( 71.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.877 ns ( 28.93 % ) " "Info: Total interconnect delay = 0.877 ns ( 28.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.031 ns" { q[2]~reg0 q[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.031 ns" { q[2]~reg0 {} q[2] {} } { 0.000ns 0.877ns } { 0.000ns 2.154ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[2]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.031 ns" { q[2]~reg0 q[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.031 ns" { q[2]~reg0 {} q[2] {} } { 0.000ns 0.877ns } { 0.000ns 2.154ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "q\[0\]~reg0 clr clk -2.938 ns register " "Info: th for register \"q\[0\]~reg0\" (data pin = \"clr\", clock pin = \"clk\") is -2.938 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.484 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 6 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.618 ns) 2.484 ns q\[0\]~reg0 3 REG LCFF_X30_Y3_N1 4 " "Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.287 ns" { clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.26 % ) " "Info: Total cell delay = 1.472 ns ( 59.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.012 ns ( 40.74 % ) " "Info: Total interconnect delay = 1.012 ns ( 40.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" { } { { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.571 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.571 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.817 ns) 0.817 ns clr 1 PIN PIN_U10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.817 ns) = 0.817 ns; Loc. = PIN_U10; Fanout = 1; PIN Node = 'clr'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.798 ns) + CELL(0.346 ns) 4.961 ns q\[0\]~62 2 COMB LCCOMB_X30_Y3_N22 6 " "Info: 2: + IC(3.798 ns) + CELL(0.346 ns) = 4.961 ns; Loc. = LCCOMB_X30_Y3_N22; Fanout = 6; COMB Node = 'q\[0\]~62'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.144 ns" { clr q[0]~62 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.213 ns) + CELL(0.397 ns) 5.571 ns q\[0\]~reg0 3 REG LCFF_X30_Y3_N1 4 " "Info: 3: + IC(0.213 ns) + CELL(0.397 ns) = 5.571 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q\[0\]~reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.610 ns" { q[0]~62 q[0]~reg0 } "NODE_NAME" } } { "counter60.v" "" { Text "F:/72_quartus_windows/test/conter60/counter60.v" 5 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.560 ns ( 28.00 % ) " "Info: Total cell delay = 1.560 ns ( 28.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.011 ns ( 72.00 % ) " "Info: Total interconnect delay = 4.011 ns ( 72.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.571 ns" { clr q[0]~62 q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.571 ns" { clr {} clr~combout {} q[0]~62 {} q[0]~reg0 {} } { 0.000ns 0.000ns 3.798ns 0.213ns } { 0.000ns 0.817ns 0.346ns 0.397ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { clk clk~clkctrl q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.484 ns" { clk {} clk~combout {} clk~clkctrl {} q[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.669ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.571 ns" { clr q[0]~62 q[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.571 ns" { clr {} clr~combout {} q[0]~62 {} q[0]~reg0 {} } { 0.000ns 0.000ns 3.798ns 0.213ns } { 0.000ns 0.817ns 0.346ns 0.397ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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