counter60.fit.summary

来自「都是高手的感受不到机房设备的发生地方时间回复是降低后付款时间的话富商大贾」· SUMMARY 代码 · 共 18 行

Fitter Status : Successful - Tue Oct 28 21:58:14 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : counter60
Top-level Entity Name : counter60
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : < 1 %
    Combinational ALUTs : 8 / 12,480 ( < 1 % )
    Dedicated logic registers : 6 / 12,480 ( < 1 % )
Total registers : 6
Total pins : 8 / 343 ( 2 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )