counter60.v

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module counter60(clk,clr,q);
input clk,clr;
output[5:0]q;
reg[5:0]q;
always@(posedge clk)
begin
if(!clr)
q<=6'b000000;
else if (q==6'b111011)
q<=6'b000000;
else
q<=q+1;
end
endmodule