counter60.tan.rpt

都是高手的感受不到机房设备的发生地方时间回复是降低后付款时间的话富商大贾

; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; q[4]~reg0 ; q[5]~reg0 ; clk        ; clk      ; None                        ; None                      ; 1.058 ns                ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tsu                                                             ;
+-------+--------------+------------+------+-----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To        ; To Clock ;
+-------+--------------+------------+------+-----------+----------+
; N/A   ; None         ; 3.177 ns   ; clr  ; q[0]~reg0 ; clk      ;
; N/A   ; None         ; 3.177 ns   ; clr  ; q[3]~reg0 ; clk      ;
; N/A   ; None         ; 3.177 ns   ; clr  ; q[4]~reg0 ; clk      ;
; N/A   ; None         ; 3.177 ns   ; clr  ; q[2]~reg0 ; clk      ;
; N/A   ; None         ; 3.177 ns   ; clr  ; q[1]~reg0 ; clk      ;
; N/A   ; None         ; 3.177 ns   ; clr  ; q[5]~reg0 ; clk      ;
+-------+--------------+------------+------+-----------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 5.609 ns   ; q[2]~reg0 ; q[2] ; clk        ;
; N/A   ; None         ; 5.171 ns   ; q[4]~reg0 ; q[4] ; clk        ;
; N/A   ; None         ; 5.156 ns   ; q[5]~reg0 ; q[5] ; clk        ;
; N/A   ; None         ; 5.143 ns   ; q[1]~reg0 ; q[1] ; clk        ;
; N/A   ; None         ; 5.134 ns   ; q[0]~reg0 ; q[0] ; clk        ;
; N/A   ; None         ; 5.112 ns   ; q[3]~reg0 ; q[3] ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -2.938 ns ; clr  ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -2.938 ns ; clr  ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -2.938 ns ; clr  ; q[4]~reg0 ; clk      ;
; N/A           ; None        ; -2.938 ns ; clr  ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -2.938 ns ; clr  ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -2.938 ns ; clr  ; q[5]~reg0 ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Oct 28 21:58:37 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off counter60 -c counter60 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "q[2]~reg0" and destination register "q[0]~reg0"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.430 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y3_N5; Fanout = 4; REG Node = 'q[2]~reg0'
            Info: 2: + IC(0.345 ns) + CELL(0.228 ns) = 0.573 ns; Loc. = LCCOMB_X30_Y3_N20; Fanout = 1; COMB Node = 'Equal0~27'
            Info: 3: + IC(0.194 ns) + CELL(0.053 ns) = 0.820 ns; Loc. = LCCOMB_X30_Y3_N22; Fanout = 6; COMB Node = 'q[0]~62'
            Info: 4: + IC(0.213 ns) + CELL(0.397 ns) = 1.430 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q[0]~reg0'
            Info: Total cell delay = 0.678 ns ( 47.41 % )
            Info: Total interconnect delay = 0.752 ns ( 52.59 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.484 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q[0]~reg0'
                Info: Total cell delay = 1.472 ns ( 59.26 % )
                Info: Total interconnect delay = 1.012 ns ( 40.74 % )
            Info: - Longest clock path from clock "clk" to source register is 2.484 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X30_Y3_N5; Fanout = 4; REG Node = 'q[2]~reg0'
                Info: Total cell delay = 1.472 ns ( 59.26 % )
                Info: Total interconnect delay = 1.012 ns ( 40.74 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "q[0]~reg0" (data pin = "clr", clock pin = "clk") is 3.177 ns
    Info: + Longest pin to register delay is 5.571 ns
        Info: 1: + IC(0.000 ns) + CELL(0.817 ns) = 0.817 ns; Loc. = PIN_U10; Fanout = 1; PIN Node = 'clr'
        Info: 2: + IC(3.798 ns) + CELL(0.346 ns) = 4.961 ns; Loc. = LCCOMB_X30_Y3_N22; Fanout = 6; COMB Node = 'q[0]~62'
        Info: 3: + IC(0.213 ns) + CELL(0.397 ns) = 5.571 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.560 ns ( 28.00 % )
        Info: Total interconnect delay = 4.011 ns ( 72.00 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.484 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.472 ns ( 59.26 % )
        Info: Total interconnect delay = 1.012 ns ( 40.74 % )
Info: tco from clock "clk" to destination pin "q[2]" through register "q[2]~reg0" is 5.609 ns
    Info: + Longest clock path from clock "clk" to source register is 2.484 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X30_Y3_N5; Fanout = 4; REG Node = 'q[2]~reg0'
        Info: Total cell delay = 1.472 ns ( 59.26 % )
        Info: Total interconnect delay = 1.012 ns ( 40.74 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 3.031 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y3_N5; Fanout = 4; REG Node = 'q[2]~reg0'
        Info: 2: + IC(0.877 ns) + CELL(2.154 ns) = 3.031 ns; Loc. = PIN_V1; Fanout = 0; PIN Node = 'q[2]'
        Info: Total cell delay = 2.154 ns ( 71.07 % )
        Info: Total interconnect delay = 0.877 ns ( 28.93 % )
Info: th for register "q[0]~reg0" (data pin = "clr", clock pin = "clk") is -2.938 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.484 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 6; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.472 ns ( 59.26 % )
        Info: Total interconnect delay = 1.012 ns ( 40.74 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.571 ns
        Info: 1: + IC(0.000 ns) + CELL(0.817 ns) = 0.817 ns; Loc. = PIN_U10; Fanout = 1; PIN Node = 'clr'
        Info: 2: + IC(3.798 ns) + CELL(0.346 ns) = 4.961 ns; Loc. = LCCOMB_X30_Y3_N22; Fanout = 6; COMB Node = 'q[0]~62'
        Info: 3: + IC(0.213 ns) + CELL(0.397 ns) = 5.571 ns; Loc. = LCFF_X30_Y3_N1; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.560 ns ( 28.00 % )
        Info: Total interconnect delay = 4.011 ns ( 72.00 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 152 megabytes of memory during processing
    Info: Processing ended: Tue Oct 28 21:58:38 2008
    Info: Elapsed time: 00:00:01