lcmpanel.h

windows mobile 6.13 dnldr下载源码

/******************************************************************
* Copyright (C), 2005-2007, HISILICON Tech. Co., Ltd.             *
*                                                                 *
* File name: lcmPanel.h                                           *
*                                                                 *
* Description:                                                    *
*     The LCM driver header file for public use.                  *
*                                                                 *
* Author:  H55798                                                 *
*                                                                 *
* Version: v0.1                                                   *
*                                                                 *
* Date:    2007.04.14                                             *
*                                                                 *
* History:                                                        *
*                                                                 *
*   1. Date:                                                      *
*      Author:                                                    *
*      Modification:                                              *
*   2. ...                                                        *
*******************************************************************/

#ifndef __LCM_PANEL_H__   /*Begin, __LCM_PANEL_H__*/
#define __LCM_PANEL_H__

#ifdef __cplusplus
extern "C" { /* allow C++ to use these headers */
#endif /* __cplusplus */


#define CLCDC_REG_RESERVED_BIT          0

/*Define the LCM panel Type*/
#define RGB_PANEL_SAMSUNG_S6D0139

#ifdef RGB_PANEL_TIANMA_HX8312A
/*
 * Define the LCM panel RS signal
 */
#define LCM_CMD_RS_SIGNAL       0

/*
 * Define the LCM panel attribution for CLCDC
 */
/*
LCDTiming0, 0x01010038
0000 0010 0000 0001 0000 0000 0011 1000
HBP = (2 - 1) = 0x01
HFP = (1 - 1) = 0
HSW = (1 - 1) = 0 
PPL = 15
    (16*(PPL + 1) = 16*(15 + 1) = 256)
*/
//#define LCD_TIMING_0_HBP    ((2 - 1) << 24)
//#define LCD_TIMING_0_HFP    ((2 - 1) << 16)
//#define LCD_TIMING_0_HSW    0   //((1 - 1) << 8) 
#define LCD_TIMING_0_HBP    ((10 - 1) << 24)    /* modified by huangjun */
#define LCD_TIMING_0_HFP    ((10 - 1) << 16)    /* modified by huangjun */
#define LCD_TIMING_0_HSW   ((10 - 1) << 8)      /* modified by jiayitao */
#define LCD_TIMING_0_PPL    ((15 - 0) << 2)  /* 16*(PPL + 1) */

/*
LCDTiming1, 0x0100013f
0000 0001 0000 0000 0000 0001 0011 1111
VBP = 1
VFP = 0
VSW = (1 - 1)
LPP = (320 - 1) = 0x13F
*/
//#define LCD_TIMING_1_VBP    ((1 - 0) << 24)
//#define LCD_TIMING_1_VFP    0   //((0 - 0) << 16)
#define LCD_TIMING_1_VFP    ((8 - 0) << 16)//((10 - 0) << 16)          /* modified by huangjun */
//#define LCD_TIMING_1_VSW    0   //((1 - 1) << 10)  
#define LCD_TIMING_1_VBP    ((8 - 0) << 24)    /* modified by huangjun */
//#define LCD_TIMING_1_VFP    ((2 - 0) << 16)     /* modified by jiayitao */
#define LCD_TIMING_1_VSW   ((10 - 1) << 10)   /* modified by jiayitao */
#define LCD_TIMING_1_LPP    ((320 - 1) << 0)

/*
LCDTiming2, 0x00EF3808
0000 0000 1110 1111 0011 1000 0000 1000
PCD_HI  = 0
BCD     = 0 // not bypass pixel clock divider
CPL     = (240 - 1)
RESERVED
IEO     = 0 // Enable is, 1 - active LOW, 0 - active HIGH
IPC     = 1 // Data is driven, 1 - on the falling edge of CLCP, 0 - on the rising edge
IHS     = 1 // Horizontal is, 1 - active LOW and inactive HIGH, 0 - active HIGH  and inactive LOW
IVS     = 1 // Vertical is, 1 - active LOW and inactive HIGH, 0 - active HIGH  and inactive LOW
ACB     = 0
CLKSEL  = 0
PCD_LO  = 8 // CLCP = CLCDCLK / (PCD + 2)
*/
#define LCD_TIMING_2_PCD_HI         0   //(0 << 27)
#define LCD_TIMING_2_BCD            0   //(0 << 26)
#define LCD_TIMING_2_CPL            ((240 - 1) << 16)
#define LCD_TIMING_2_RESERVED       0   //(0 << 15)   
#define LCD_TIMING_2_IEO            0   //(0 << 14)
#define LCD_TIMING_2_IPC            (1 << 13)
#define LCD_TIMING_2_IHS            (1 << 12)
#define LCD_TIMING_2_IVS            (1 << 11)
#define LCD_TIMING_2_ACB            0   //(0 << 6)
#define LCD_TIMING_2_CLKSEL         0   //(0 << 5)
//#define LCD_TIMING_2_PCD_LO         (8 << 0)
#define LCD_TIMING_2_PCD_LO         (18 << 0)   /* modified by huangjun */

/*
LCDTiming3, 0x0

RESERVED
LEE = 0
RESERVED
LED = 0
*/
#define LCD_TIMING_3_LEE            0   //(0 << 16)
#define LCD_TIMING_3_LED            0   //(0 << 0)

/*
LCDControl, 0x00000829
0000 0000 0000 0000 0000 1000 0010 1001

RESERVED
WATERMARK   0
RESERVED
LCDVCOMP    0
LCDPWR      1
BEPO        0
BEBO        0
BGR         0
LCDDUAL     0
LCDMONO8    0
LCDTFT      1
LCDBW       0
LCDBPP      4
LCDEN       0   //  default not enable CLCDC, this bit is controlled by clcdcSwitch function
*/
#define LCD_CONTROL_WATERMARK       0   //(0 << 16)
#define LCD_CONTROL_LCDVCOMP        0   //(0 << 12)
#define LCD_CONTROL_LCDPWR          (1 << 11)
#define LCD_CONTROL_BEPO            0   //(0 << 10)
#define LCD_CONTROL_BEBO            0   //(0 << 9)
#define LCD_CONTROL_BGR             0   //(0 << 8)
#define LCD_CONTROL_LCDDUAL         0   //(0 << 7)
#define LCD_CONTROL_LCDMONO8        0   //(0 << 6)    
#define LCD_CONTROL_LCDTFT          (1 << 5)
#define LCD_CONTROL_LCDBW           0   //(0 << 4)
#define LCD_CONTROL_LCDBPP          (4 << 1)	//(5 << 1)	//RGB666	01010
#define LCD_CONTROL_LCDEN_0         0   //(0 << 0)

/*
 * Define image display informaion  
 */

#define PANEL_DISPLAY_BPP                16


#define PANEL_DISPLAY_WIDTH              240

#define PANEL_DISPLAY_HEIGHT             320


#endif /*End, RGB_PANEL_TIANMA_HX8312A*/


#ifdef RGB_PANEL_SAMSUNG_S6D0139 /*Begin, RGB_PANEL_SAMSUNG_S6D0139*/
/*
 * Define the LCM panel RS signal
 */
#define LCM_CMD_RS_SIGNAL       0
//#ifndef 0

/*
 * Define the LCM panel attribution for CLCDC
 */
/*
LCDTiming0, 0x01010038
0000 0010 0000 0001 0000 0000 0011 1000
HBP = (2 - 1) = 0x01
HFP = (1 - 1) = 0
HSW = (1 - 1) = 0 
PPL = 15
    (16*(PPL + 1) = 16*(15 + 1) = 256)
*/
//#define LCD_TIMING_0_HBP    ((2 - 1) << 24)
//#define LCD_TIMING_0_HFP    ((2 - 1) << 16)
//#define LCD_TIMING_0_HSW    0   //((1 - 1) << 8) 
#define LCD_TIMING_0_HBP    ((8 - 1) << 24)    
#define LCD_TIMING_0_HFP    ((8 - 1) << 16)   
#define LCD_TIMING_0_HSW   ((4 - 1) << 8)     //HWL = 4 DOTCLK
#define LCD_TIMING_0_PPL    ((14 - 0) << 2)  /* 16*(PPL + 1) *///240

/*
LCDTiming1, 0x0100013f
0000 0001 0000 0000 0000 0001 0011 1111
VBP = 1
VFP = 0
VSW = (1 - 1)
LPP = (320 - 1) = 0x13F
*/
//#define LCD_TIMING_1_VBP    ((1 - 0) << 24)
//#define LCD_TIMING_1_VFP    0   //((0 - 0) << 16)
#define LCD_TIMING_1_VBP    ((8 - 0) << 24)   
#define LCD_TIMING_1_VFP    ((8- 0) << 16)          
//#define LCD_TIMING_1_VSW    0   //((1 - 1) << 10)  
 
//#define LCD_TIMING_1_VFP    ((2 - 0) << 16)    
#define LCD_TIMING_1_VSW   ((3 - 0) << 10) // VWL >= 1 HSYNC
#define LCD_TIMING_1_LPP    ((320 - 1) << 0)

/*
LCDTiming2, 0x00EF3808
0000 0000 1110 1111 0011 1000 0000 1000
PCD_HI  = 0
BCD     = 0 // not bypass pixel clock divider
CPL     = (240 - 1)
RESERVED
IEO     = 0 // Enable is, 1 - active LOW, 0 - active HIGH
IPC     = 1 // Data is driven, 1 - on the falling edge of CLCP, 0 - on the rising edge
IHS     = 1 // Horizontal is, 1 - active LOW and inactive HIGH, 0 - active HIGH  and inactive LOW
IVS     = 1 // Vertical is, 1 - active LOW and inactive HIGH, 0 - active HIGH  and inactive LOW
ACB     = 0
CLKSEL  = 0
PCD_LO  = 8 // CLCP = CLCDCLK / (PCD + 2)
*/
#define LCD_TIMING_2_PCD_HI         0   //(0 << 27)
#define LCD_TIMING_2_BCD            0   //(0 << 26)
#define LCD_TIMING_2_CPL            ((240 - 1) << 16)
#define LCD_TIMING_2_RESERVED       0   //(0 << 15)   
#define LCD_TIMING_2_IEO            (1 << 14)   //(0 << 14)
#define LCD_TIMING_2_IPC            (1<< 13)
#define LCD_TIMING_2_IHS            (1 << 12)
#define LCD_TIMING_2_IVS            (1 << 11)
#define LCD_TIMING_2_ACB            0   //(0 << 6)
#define LCD_TIMING_2_CLKSEL         0   //(0 << 5)
#define LCD_TIMING_2_PCD_LO         (8 << 0)/*(4<< 0)*/

/*
LCDTiming3, 0x0

RESERVED
LEE = 0
RESERVED
LED = 0
*/
#define LCD_TIMING_3_LEE            0   //(0 << 16)
#define LCD_TIMING_3_LED            0   //(0 << 0)

/*
LCDControl, 0x00000829
0000 0000 0000 0000 0000 1000 0010 1001

RESERVED
WATERMARK   0
RESERVED
LCDVCOMP    0
LCDPWR      1
BEPO        0
BEBO        0
BGR         0
LCDDUAL     0
LCDMONO8    0
LCDTFT      1
LCDBW       0
LCDBPP      4
LCDEN       0   //  default not enable CLCDC, this bit is controlled by clcdcSwitch function
*/
#define LCD_CONTROL_WATERMARK       0   //(0 << 16)
#define LCD_CONTROL_LCDVCOMP        (0 << 12) //(0 << 12) /* modified by huangjun */
#define LCD_CONTROL_LCDPWR          (1 << 11)
#define LCD_CONTROL_BEPO            0   //(0 << 10)
#define LCD_CONTROL_BEBO            0   //(0 << 9)
#define LCD_CONTROL_BGR             0   //(0 << 8)
#define LCD_CONTROL_LCDDUAL         0   //(0 << 7)
#define LCD_CONTROL_LCDMONO8        0   //(0 << 6)    
#define LCD_CONTROL_LCDTFT          (1 << 5)
#define LCD_CONTROL_LCDBW           0   //(0 << 4)
#define LCD_CONTROL_LCDBPP          (6 << 1)	//RGB666	01010
#define LCD_CONTROL_LCDEN_0         0   //(0 << 0)

/*
 * Define image display informaion  
 */

#define PANEL_DISPLAY_BPP           16

#define PANEL_DISPLAY_WIDTH         240

#define PANEL_DISPLAY_HEIGHT        320


#endif /*End, RGB_PANEL_SAMSUNG_S6D0139*/

/*Define CLCDC registers setting value*/
#define VAL_CLCDC_TIMING_0      ( LCD_TIMING_0_HBP | \
                                  LCD_TIMING_0_HFP | \
                                  LCD_TIMING_0_HSW | \
                                  LCD_TIMING_0_PPL )
                                  
#define VAL_CLCDC_TIMING_1      ( LCD_TIMING_1_VBP | \
                                  LCD_TIMING_1_VFP | \
                                  LCD_TIMING_1_VSW | \
                                  LCD_TIMING_1_LPP )


#define VAL_CLCDC_TIMING_2      ( LCD_TIMING_2_PCD_HI   | \
                                  LCD_TIMING_2_BCD      | \
                                  LCD_TIMING_2_CPL      | \
                                  LCD_TIMING_2_RESERVED | \
                                  LCD_TIMING_2_IEO      | \
                                  LCD_TIMING_2_IPC      | \
                                  LCD_TIMING_2_IHS      | \
                                  LCD_TIMING_2_IVS      | \
                                  LCD_TIMING_2_ACB      | \
                                  LCD_TIMING_2_CLKSEL )          

#define VAL_CLCDC_TIMING_3      ( LCD_TIMING_3_LEE | \
                                  LCD_TIMING_3_LED )

#define VAL_CLCDC_CONTROL       ( LCD_CONTROL_WATERMARK |\
                                  LCD_CONTROL_LCDVCOMP  |\
                                  LCD_CONTROL_LCDPWR    |\
                                  LCD_CONTROL_BEPO      |\
                                  LCD_CONTROL_BEBO      |\
                                  LCD_CONTROL_BGR       |\
                                  LCD_CONTROL_LCDDUAL   |\
                                  LCD_CONTROL_LCDMONO8  |\
                                  LCD_CONTROL_LCDTFT    |\
                                  LCD_CONTROL_LCDBW     |\
                                  LCD_CONTROL_LCDBPP    |\
                                  LCD_CONTROL_LCDEN_0 )

/*Define LCM display parameters*/

#define LCM_DISPLAY_BPP             PANEL_DISPLAY_BPP

#define LCM_DISPLAY_WIDTH           PANEL_DISPLAY_WIDTH

#define LCM_DISPLAY_HEIGHT          PANEL_DISPLAY_HEIGHT

#define LCM_MAIN_SCREEN             0
#define LCM_SUB_SCREEN              1

#ifdef __cplusplus
} /* allow C++ to use these headers */
#endif /* __cplusplus */

#endif  /*End, __LCM_PANEL_H__*/