uartreg.h

windows mobile 6.13 dnldr下载源码

/*******************************************************************************
 * Copyright:   Copyright (c) 2007. Hisilicon Technologies, CO., LTD. 
 * Version:     V300R001B04
 * Filename:    UARTReg.h
 * Description: Uart的寄存器定义
 * History:
                1.Created by SunShaoJie on 2007/12/25
*******************************************************************************/
#ifndef UART_REG_H
#define UART_REG_H

/*equates for receive status register*/
#define UART_RSR_FE     0x01
#define UART_RSR_PE     0x02
#define UART_RSR_BE     0x04
#define UART_RSR_OE     0x08

/*equates for flag register*/
#define UART_FR_CTS     0x0001
#define UART_FR_DSR     0x0002
#define UART_FR_DCD     0x0004
#define UART_FR_BUSY    0x0008
#define UART_FR_RXFE    0x0010
#define UART_FR_TXFF    0x0020
#define UART_FR_RXFF    0x0040
#define UART_FR_TXFE    0x0080
#define UART_FR_RI      0x0100

/*equates for line control register*/
#define UART_LCR_BRK    0x01
#define UART_LCR_PEN    0x02
#define UART_LCR_PDIS   0x00
#define UART_LCR_EPS    0x04
#define UART_LCR_STP2   0x08
#define UART_LCR_FEN    0x10
#define UART_LCR_WLS    0x60
#define UART_LCR_WLS8   0x60
#define UART_LCR_WLS7   0x40
#define UART_LCR_WLS6   0x20
#define UART_LCR_WLS5   0x00
#define UART_LCR_CS8    0x60
#define UART_LCR_CS7    0x40
#define UART_LCR_CS6    0x20
#define UART_LCR_CS5    0x00
#define UART_LCR_SPS    0x80

/* equates for control  register(CR) */
#define UART_CR_UARTEN  0x0001   
#define UART_CR_SIREN   0x0002  
#define UART_CR_SIRLP   0x0004
#define UART_CR_LBE     0x0080    
#define UART_CR_TXE     0x0100
#define UART_CR_RXE     0x0200
#define UART_CR_DTR     0x0400
#define UART_CR_RTS     0x0800
#define UART_CR_OUT1    0x1000
#define UART_CR_OUT2    0x2000
#define UART_CR_RTSEn   0x4000
#define UART_CR_CTSEn   0x8000

/*equates for fifo reg*/
#define UART_IFLS_RXIFLSEL   0x38
#define UART_IFLS_RXMASK     0x38    /* transmit fifo bits mask */
#define UART_IFLS_RXTL2      0x00    /* transmit fifo trigger level 2byte */
#define UART_IFLS_RXTL4      0x08    /* transmit fifo trigger level 4byte */
#define UART_IFLS_RXTL8      0x10    /* transmit fifo trigger level 8byte */
#define UART_IFLS_RXTL12     0x18    /* transmit fifo trigger level 12byte */
#define UART_IFLS_RXTL14     0x20    /* transmit fifo trigger level 14byte */

#define UART_IFLS_TXIFLSEL   0x07
#define UART_IFLS_TXMASK     0x07    /* receive fifo bits mask */
#define UART_IFLS_TXTL2      0x00    /* receive fifo trigger level 2byte */
#define UART_IFLS_TXTL4      0x01    /* receive fifo trigger level 4byte */
#define UART_IFLS_TXTL8      0x02    /* receive fifo trigger level 8byte */
#define UART_IFLS_TXTL12     0x03    /* receive fifo trigger level 12byte */
#define UART_IFLS_TXTL14     0x04    /* receive fifo trigger level 14byte */

/*equates for interrupt mask set clear register*/
#define UART_IMSC_MASK       0x07FF
#define UART_IMSC_ENABLEALL  0x07FF
#define UART_IMSC_DISABLEALL 0x0000
#define UART_IMSC_MSTAT      0x000F
#define UART_IMSC_RIMIM      0x0001
#define UART_IMSC_CTSMIM     0x0002
#define UART_IMSC_DCDMIM     0x0004
#define UART_IMSC_DSRMIM     0x0008
#define UART_IMSC_RXIM       0x0010
#define UART_IMSC_TXIM       0x0020
#define UART_IMSC_RTIM       0x0040
#define UART_IMSC_FEIM       0x0080
#define UART_IMSC_PEIM       0x0100
#define UART_IMSC_BEIM       0x0200
#define UART_IMSC_OEIM       0x0400

/*equates for Raw interrupt STATUS register*/
#define UART_RIS_RIRMIS      0x0001
#define UART_RIS_CTSRMIS     0x0002
#define UART_RIS_DCDRMIS     0x0004
#define UART_RIS_DSRRMIS     0x0008
#define UART_RIS_RXRIS       0x0010
#define UART_RIS_TXRIS       0x0020
#define UART_RIS_RTRIS       0x0040
#define UART_RIS_FERIS       0x0080
#define UART_RIS_PERIS       0x0100
#define UART_RIS_BERIS       0x0200
#define UART_RIS_OERIS       0x0400

/*equates for masked interrupt status register*/
#define UART_MIS_MASK        0x07FF
#define UART_MIS_MSMASK      0x000F
#define UART_MIS_ERMASK      0x0780
#define UART_MIS_RIMMIS      0x0001
#define UART_MIS_CTSMMIS     0x0002
#define UART_MIS_DCDMMIS     0x0004
#define UART_MIS_DSRMMIS     0x0008
#define UART_MIS_RXMIS       0x0010
#define UART_MIS_TXMIS       0x0020
#define UART_MIS_RTMIS       0x0040
#define UART_MIS_FEMIS       0x0080
#define UART_MIS_PEMIS       0x0100
#define UART_MIS_BEMIS       0x0200
#define UART_MIS_OEMIS       0x0400

/*equates for interrupt clear register*/
#define UART_ICR_RIMIC       0x0001
#define UART_ICR_CTSMIC      0x0002
#define UART_ICR_DCDMIC      0x0004
#define UART_ICR_DSRMIC      0x0008
#define UART_ICR_RXIC        0x0010
#define UART_ICR_TXIC        0x0020
#define UART_ICR_RTIC        0x0040
#define UART_ICR_FEIC        0x0080
#define UART_ICR_PEIC        0x0100
#define UART_ICR_BEIC        0x0200
#define UART_ICR_OEIC        0x0400

/* UART register */
/* General register adress definitions */
#define UART_RFR    0x000    /* Receive Fifo reg.    */
#define UART_TFR    0x000    /* Transmit Fifo reg.   */
#define UART_RSR    0x004    /* receive status register   */
#define UART_ECR    0x004    /* error clear reg*/
#define UART_FR     0x018    /*flag register*/
#define UART_ILPR   0x020    /*IrDA low power register*/
#define UART_IBRD   0x024    /*Integer baud rate dividor*/
#define UART_FBRD   0x028    /*fractional baud rate dividor*/
#define UART_LCR    0x02c    /* line control reg */
#define UART_CR     0x030    /* control reg */
#define UART_IFLS   0x034    /*interrupt level select register*/
#define UART_IMSC   0x038    /*interrupt mask set clear register*/
#define UART_RIS    0x03c    /*raw interrupt status register*/
#define UART_MIS    0x040    /*masked interrupt status register*/
#define UART_ICR    0x044    /*interrupt clear register*/
#define UART_DMACR  0x048    /*DMA control register*/

#endif