📄 pl110_clcdc.h
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/******************************************************************
* Copyright (C), 2005-2007, HISILICON Tech. Co., Ltd. *
* *
* File name: pl110_clcdc.h *
* *
* Description: *
* The CLCDC driver header file for public use. *
* *
* Author: H55798 *
* *
* Version: v0.1 *
* *
* Date: 2007.04.14 *
* *
* History: *
* *
* 1. Date: *
* Author: *
* Modification: *
* 2. ... *
*******************************************************************/
#ifndef __PL110_CLCDC_H__ /*Begin, __PL110_CLCDC_H__*/
#define __PL110_CLCDC_H__
#ifdef __cplusplus
extern "C" { /* allow C++ to use these headers */
#endif /* __cplusplus */
#include "Register.h"
#define DISPLAY_INITIAL_CALLER_SYS 0
#define DISPLAY_INITIAL_CALLER_OAL 1
#define CLCDC_DEBUG 0
#define CLCDC_ERR_DEBUG 1
// EDC
/* Regs Of Graphic Layer */
#define EDC_GRP_ADDR 0x04
#define EDC_GRP_LN_OFFSET 0x08
#define EDC_GRP_XY 0x0C
#define EDC_GRP_SIZE 0x10
#define EDC_GRP_CTL 0x14
#define EDC_GRP_COLORK_MIN 0x18
#define EDC_GRP_COLORK_MAX 0x1C
#define EDC_GRP_ALP_VAL 0x20
/* Regs Of Video Layer */
#define EDC_YRGB_ADDR 0x24
#define EDC_UV_ADDR 0x28
#define EDC_V_ADDR 0x2C
#define EDC_VIDEO_LN_OFFSET 0x30
#define EDC_VIDEO_XY 0x34
#define EDC_VIDEO_SIZE 0x38
#define EDC_VIDEO_CTL 0x3C
/* Regs Of Video Scaler */
#define EDC_VIDEO_COLORK_MIN 0x40
#define EDC_VIDEO_COLORK_MAX 0x44
#define EDC_SCL_PRM_HRZ 0x48
#define EDC_SCL_PRM_VRT 0x4C
#define EDC_SCL_SIZE 0x50
/* Regs Of Cursor Lay */
#define EDC_CRS_ADDR 0x54
#define EDC_CRS_XY 0x58
#define EDC_CRS_CTL 0x5C
#define EDC_CRS_COLOR1 0x60
#define EDC_CRS_COLOR2 0x64
/* Regs Of Display Config */
#define EDC_DISP_SIZE 0x68
#define EDC_DISP_CTL 0x6C
/* Regs Of Interrrupt/Status */
#define EDC_STS 0x70
#define EDC_INTS 0x74
#define EDC_INTE 0x78
#define EDC_DEBUG 0x7C
/* Mask of EDC_GRP_LN_OFFSET */
#define GRP_LN_OFFSET_MASK 0x00000FFF
/* Mask & shift of EDC_GRP_XY */
#define GRP_X_MASK 0x03FF0000
#define GRP_X_SHIFT 0x10
#define GRP_Y_MASK 0x000003FF
#define GRP_Y_SHIFT 0x0
/* Mask & shift of EDC_GRP_SIZE */
#define GRP_SIZE_HRZ_MASK 0x03FF0000
#define GRP_SIZE_HRZ_SHIFT 0x10
#define GRP_SIZE_VRT_MASK 0x000003FF
#define GRP_SIZE_VRT_SHIFT 0x0
/* Field Of EDC_GRP_CTL */
#define GRP_EN (1<<27)
#define GRP_TOP (1<<26)
#define GRP_ROT_0 (0<<24)
#define GRP_ROT_90 (2<<24)
#define GRP_ROT_270 (3<<24)
#define GRP_SRC_BLEND_EN (1<<23)
#define GRP_ALP_SRC_GLOBAL (1<<22)
#define GRP_ALP_SRC_PIXEL (0<<22)
#define GRP_ALP_INV (1<<21)
#define GRP_DES_COLORK_EN (1<<20)
#define GRP_BGR (1<<19)
#define GRP_RGBIN_RGB565 (0<<16)
#define GRP_RGBIN_RGB888 (1<<16)
#define GRP_RGBIN_RGB4444 (4<<16)
#define GRP_RGBIN_RGB1555 (5<<16)
#define GRP_RGBIN_RGB8888 (6<<16)
#define GRP_SECU_LINE_MASK 0x000003FF
#define GRP_SECU_LINE_SHIFT 0x0
/* Mask & shift of EDC_DISP_SIZE */
#define DISP_SIZE_HRZ_MASK 0x03FF0000
#define DISP_SIZE_HRZ_SHIFT 0x10
#define DISP_SIZE_VRT_MASK 0x000003FF
#define DISP_SIZE_VRT_SHIFT 0x0
/* Field of EDC_DISP_CTL */
#define DISP_EN (1<<22)
#define DISP_ENDIAN_LITTLE (0<<19)
#define DISP_RGB (0<<18)
#define DISP_BGR (1<<18)
#define DISP_PIX_FMT_RGB565 (0<<16)
#define DISP_PIX_FMT_RGB666 (1<<16)
#define DISP_DPD_MASK 0x0000FFFF
#define DISP_DPD_SHIFT 0x0
/* Mask & shift of EDC_DEBUG */
#define CLFP_SEL (1 << 30)
#define CLFP_INV (1 << 29)
//-------------------------------------------------------------------------------------------
/************************************************
*
* Define CLCDC Related Macro and Structure
*
************************************************/
/*
* Define CLCDC Device Registers Address
*/
#define CLCDC_LCDTIMING_0_REG (SYS_CLCDC_BASE_ADDRESS + 0x00)
#define CLCDC_LCDTIMING_1_REG (SYS_CLCDC_BASE_ADDRESS + 0x04)
#define CLCDC_LCDTIMING_2_REG (SYS_CLCDC_BASE_ADDRESS + 0x08)
#define CLCDC_LCDTIMING_3_REG (SYS_CLCDC_BASE_ADDRESS + 0x0C)
#define CLCDC_LCDUPBASE_REG (SYS_CLCDC_BASE_ADDRESS + 0x10)
#define CLCDC_LCDLPBASE_REG (SYS_CLCDC_BASE_ADDRESS + 0x14)
#define CLCDC_LCDIMSC_REG (SYS_CLCDC_BASE_ADDRESS + 0x18)
#define CLCDC_LCDCONTROL_REG (SYS_CLCDC_BASE_ADDRESS + 0x1C)
#define CLCDC_LCDRIS_REG (SYS_CLCDC_BASE_ADDRESS + 0x20)
#define CLCDC_LCDMIS_REG (SYS_CLCDC_BASE_ADDRESS + 0x24)
#define CLCDC_LCDICR_REG (SYS_CLCDC_BASE_ADDRESS + 0x28)
#define CLCDC_LCDUPCURR_REG (SYS_CLCDC_BASE_ADDRESS + 0x2C)
#define CLCDC_LCDLPCURR_REG (SYS_CLCDC_BASE_ADDRESS + 0x30)
#define CLCDC_LCDPALETTE_REG (SYS_CLCDC_BASE_ADDRESS + 0x200)
/*
* CLCDC Frame Buffer write 1Byte, 2Bytes, 4Bytes, and endianness set
*/
#define CLCDC_FRAMEBUFFER_ALIGN_NO 0
#define CLCDC_FRAMEBUFFER_ALIGN_BYTE2 2
#define CLCDC_FRAMEBUFFER_ALIGN_BYTE4 4
#define CLCDC_PICTURE_IS_LITTLE_ENDIAN 0
#define CLCDC_PICTURE_IS_BIG_ENDIAN 1
/*
* Define CLCDC_LCDTIMING_0_REG register bit operation field
*/
#define bsLCDTiming0REV0 ((UINT32) 2)
#define bwLCDTiming0REV0 ((UINT32) 6)
#define bsLCDTiming0PPL ((UINT32) 2)
#define bwLCDTiming0PPL ((UINT32) 6)
#define bsLCDTiming0HSW ((UINT32) 8)
#define bwLCDTiming0HSW ((UINT32) 8)
#define bsLCDTiming0HFP ((UINT32) 16)
#define bwLCDTiming0HFP ((UINT32) 8)
#define bsLCDTiming0HBP ((UINT32) 24)
#define bwLCDTiming0HBP ((UINT32) 8)
/*
* Define CLCDC_LCDTIMING_1_REG register bit operation field
*/
#define bsLCDTiming1LPP ((UINT32) 0)
#define bwLCDTiming1LPP ((UINT32) 10)
#define bsLCDTiming1VSW ((UINT32) 10)
#define bwLCDTiming1VSW ((UINT32) 6)
#define bsLCDTiming1VFP ((UINT32) 16)
#define bwLCDTiming1VFP ((UINT32) 8)
#define bsLCDTiming1VBP ((UINT32) 24)
#define bwLCDTiming1VBP ((UINT32) 8)
/*
* Define CLCDC_LCDTIMING_2_REG register bit operation field
*/
#define bsLCDTiming2PCDLO ((UINT32) 0)
#define bwLCDTiming2PCDLO ((UINT32) 5)
#define bsLCDTiming2CLKSEL ((UINT32) 5)
#define bwLCDTiming2CLKSEL ((UINT32) 1)
#define bsLCDTiming2ACB ((UINT32) 6)
#define bwLCDTiming2ACB ((UINT32) 5)
#define bsLCDTiming2IVS ((UINT32) 11)
#define bwLCDTiming2IVS ((UINT32) 1)
#define bsLCDTiming2IHS ((UINT32) 12)
#define bwLCDTiming2IHS ((UINT32) 1)
#define bsLCDTiming2IPC ((UINT32) 13)
#define bwLCDTiming2IPC ((UINT32) 1)
#define bsLCDTiming2IEO ((UINT32) 14)
#define bwLCDTiming2IEO ((UINT32) 1)
#define bsLCDTiming2REV0 ((UINT32) 15)
#define bwLCDTiming2REV0 ((UINT32) 1)
#define bsLCDTiming2CPL ((UINT32) 16)
#define bwLCDTiming2CPL ((UINT32) 10)
#define bsLCDTiming2BCD ((UINT32) 26)
#define bwLCDTiming2BCD ((UINT32) 1)
#define bsLCDTiming2PCDHI ((UINT32) 27)
#define bwLCDTiming2PCDHI ((UINT32) 5)
/*
* Define CLCDC_LCDTIMING_3_REG register bit operation field
*/
#define bsLCDTiming3LED ((UINT32) 0)
#define bwLCDTiming3LED ((UINT32) 7)
#define bsLCDTiming3REV0 ((UINT32) 7)
#define bwLCDTiming3REV0 ((UINT32) 9)
#define bsLCDTiming3LEE ((UINT32) 16)
#define bwLCDTiming3LEE ((UINT32) 1)
#define bsLCDTiming3REV1 ((UINT32) 17)
#define bwLCDTiming3REV1 ((UINT32) 15)
/*
* Define CLCDC_UPBASE_REG register bit operation field
*/
#define bsLCDUpBase ((UINT32) 2)
#define bwLCDUpBase ((UINT32) 30)
/*
* Define CLCDC_LPBASE_REG register bit operation field
*/
#define bsLCDLpBase ((UINT32) 2)
#define bwLCDLpBase ((UINT32) 30)
/*
* Define CLCDC_IMSC_REG register bit operation field
*/
#define bsLCDIMSCFUFInt ((UINT32) 1)
#define bwLCDIMSCFUFInt ((UINT32) 1)
#define bsLCDIMSCLNBUInt ((UINT32) 2)
#define bwLCDIMSCLNBUInt ((UINT32) 1)
#define bsLCDIMSCVCOMPInt ((UINT32) 3)
#define bwLCDIMSCVCOMPInt ((UINT32) 1)
#define bsLCDIMSCMBErrInt ((UINT32) 4)
#define bwLCDIMSCMBErrInt ((UINT32) 1)
#define CLCDC_FUF_INT 0x2
#define CLCDC_LNBU_INT 0x4
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