shifter_n.vhdl

fft that uses the cordic alghoritm---5

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity shifter_n is
	generic(
		N :natural :=16
	);
	port(                                
 	   	iShtIn : in std_logic;
 	   	irst : in std_logic;
 	   	iclk : in std_logic;
		------------------------------
		oShtOut : out std_logic_vector(N-1 downto 0)
	);
end shifter_n;                            

architecture behave of shifter_n is


component shifter_1 is
	port(                                
 	   	iShtIn1 : in std_logic;
 	   	irst : in std_logic;
 	   	iclk : in std_logic;
		------------------------------
		oShtOut1 : out std_logic

	);
end component;   

signal sCarry: std_logic_vector (N downto 0); 
signal oout:std_logic_vector(N-1 downto 0);
begin

--shiftere de un bit instantiate
G: for i in 0 to N-1 generate
SUM : shifter_1
	port map(
	irst => irst,
	iShtIn1 => sCARRY(i),
	oShtOut1 => sCARRY(i+1),
	iclk => iclk
	);
end generate;

sCarry(0)<=iShtIn;


oout(N-1 downto 0) <= sCarry(N downto 1);
oShtOut<=oout;
end behave;