shifter_n_load.vhdl

fft that uses the cordic alghoritm---5

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity shifter_n_load is
	generic(
		N :natural :=16
	);
	port(                                
 	   	iShtIn : in std_logic;
 	   	irst : in std_logic;
 	   	iclk : in std_logic;
 	   	iload: in std_logic;
 	   	iLoadIN: in std_logic_vector(N-1 downto 0);
		------------------------------
		oShtOut : out std_logic_vector(N-1 downto 0)

	);
end shifter_n_load;                            

architecture behave of shifter_n_load is


component shifter_1_load is
	port(                                
 	   	iShtIn1 : in std_logic;
 	   	irst : in std_logic;
 	   	iclk : in std_logic;
 	   	iload: in std_logic;
 	   	iShtLoadIn: in std_logic;
		------------------------------
		oShtOut1 : out std_logic
	);
end component;   

signal sCarry: std_logic_vector (N downto 0); 
begin

--shiftere de un bit instantiate +++load!!!
G: for i in 0 to N-1 generate
	SUM : shifter_1_load
	port map(
	irst => irst,
	iShtIn1 => sCARRY(i),
	oShtOut1 => sCARRY(i+1),
	iclk => iclk,
	iload=> iload,
	iShtLOadIn=> iLoadIn(i)
	);
end generate;

sCarry(0)<=iShtIn;


oShtOut(N-1 downto 0) <= sCarry(N downto 1);
end behave;