shifter_1_load.vhdl

fft that uses the cordic alghoritm---4

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity shifter_1_load is
	port(                                
 	   	iShtIn1    : in std_logic;
 	   	irst 	   : in std_logic;
 	   	iclk 	   : in std_logic;
 	   	iload	   : in std_logic;
 	   	iShtLoadIn : in std_logic;
		------------------------------
		oShtOut1   : out std_logic

	);
end shifter_1_load;                            


architecture behave of shifter_1_load is

begin

	process (irst, iclk, iload, ishtloadin, ishtin1)
	begin
		if irst='1' then
			oShtOut1 <= '0';
		else	
			if iload='1' then
				oShtOut1 <= iShtLoadIn;
			elsif rising_edge(iclk) then
				oShtOut1 <= iShtIn1;
			end if;
		end if;
	end process;

end behave;