shifter_1.vhdl

fft that uses the cordic alghoritm---4

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity shifter_1 is
	port(                                
 	   	iShtIn1  : in std_logic;
 	   	irst     : in std_logic;
 	   	iclk     : in std_logic;
		------------------------------
		oShtOut1 : out std_logic

	);
end shifter_1;                            


architecture behave of shifter_1 is

begin

	process (irst, iclk)
	begin
		if irst='1' then
			oShtOut1 <= '0';
		else	
			if rising_edge(iclk) then
				oShtOut1 <= iShtIn1;
			end if;
		end if;
	end process;

end behave;