sequence_detector_tx.vhd

fft that uses the cordic alghoritm---3

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sequence_detector_tx is
port  ( clk2MHz, reset, signal_in      : in  std_logic;
        sequence_found                 : out std_logic 
       );
end sequence_detector_tx;


architecture rtl_tx of sequence_detector_tx is

type   state_fsm is (idle, ignore, T1st, check_T1, clr_cnt1, T2st, clr_cnt2, check_T2, T3st, check_T3, found_seq);
constant sh_const_rise    			    : std_logic_vector (3 downto 0)  := "0111"; 
constant sh_const_fall    			    : std_logic_vector (3 downto 0)  := "1000";
constant  T1min           			    : std_logic_vector (7 downto 0)  := "00000110"; --3 us  - 6    - clk 2MHz
constant  T1max           			    : std_logic_vector (7 downto 0)  := "00001000"; --4 us  - 8    - clk 2MHz
constant  T2min           			    : std_logic_vector (7 downto 0)  := "00010111"; --8 us  - 23   - clk 2MHz   
constant  T2max           			    : std_logic_vector (7 downto 0)  := "00011001"; --9 us  - 25   - clk 2MHz   
constant  T3min           			    : std_logic_vector (7 downto 0)  := "00000110"; --3 us  - 6    - clk 2MHz   
constant  T3max           			    : std_logic_vector (7 downto 0)  := "00001000"; --4 us  - 8    - clk 2MHz
constant  Tretardatie   				: std_logic_vector (7 downto 0)  := "01100100"; --50 us - 100  - clk 2MHz
signal pst_state, nxt_state             : state_fsm;
signal counter_1, counter_2		        : std_logic_vector (7 downto 0);
signal T1inlimit, T2inlimit, T3inlimit  : std_logic;
signal sync_counter_1, enable_counter_1 : std_logic;
signal sync_counter_2, enable_counter_2 : std_logic;
signal signal_in_up, signal_in_down     : std_logic;
signal shreg_s            			    : std_logic_vector (3 downto 0);

begin


-- doua countere
counter8b1: process (clk2MHz, reset)
begin
 if (reset = '1') then 
 	 counter_1 <= "00000000";
 elsif rising_edge (clk2MHz) then 
  	 if (sync_counter_1 = '1') then 
  		counter_1 <= "00000000";
     elsif (enable_counter_1 = '1') then 
        counter_1 <= counter_1 + '1';
     end if;  
 end if;
end process;

counter8b2: process (clk2MHz, reset)
begin
 if (reset = '1') then 
 	 counter_2 <= "00000000";
 elsif rising_edge (clk2MHz) then 
  	 if (sync_counter_2 = '1') then 
  		counter_2 <= "00000000";
     elsif (enable_counter_2 = '1') then 
        counter_2 <= counter_2 + '1';
     end if;  
 end if;
end process;


T1inlimit <= '1' when ((counter_1 >= T1min) and (counter_1 <= T1max)) else '0';
T2inlimit <= '1' when ((counter_2 >= T2min) and (counter_2 <= T2max)) else '0';
T3inlimit <= '1' when ((counter_1 >= T3min) and (counter_1 <= T3max)) else '0';



shreg:process (clk2MHz, reset)
begin
 if (reset = '1') then 
 	 shreg_s <= (others =>'0');
 elsif rising_edge (clk2MHz) then 
 	 shreg_s <= shreg_s (shreg_s'left-1 downto 0) & signal_in;
 end if;   
end process;


signal_in_up   <= '1' when (shreg_s = sh_const_rise) else '0'; 
signal_in_down <= '1' when (shreg_s = sh_const_fall) else '0'; 


chg_state: process (clk2MHz, reset)
begin
 if (reset = '1') then pst_state <= idle;
  elsif rising_edge (clk2MHz) then pst_state <= nxt_state;
 end if;
end process;


seq_det: process (pst_state, signal_in_up, signal_in_down, T1inlimit, T2inlimit, T3inlimit)
begin
 case pst_state is
  when idle     => if (signal_in_up = '1') then nxt_state <= T1st; 
                    else nxt_state <= idle;
                   end if;

  when T1st     => if (signal_in_down = '1') then nxt_state <= check_T1; 
                    else nxt_state <= T1st;
                   end if;

  when check_T1 => if (T1inlimit = '1') then nxt_state <= clr_cnt1;
                    else nxt_state <= ignore;
                   end if; 

  when clr_cnt1 => nxt_state <= T2st; 

  when T2st     => if (signal_in_up = '1') then nxt_state <= check_T2; 
                    else nxt_state <= T2st;
                   end if; 

  when check_T2 => if (T2inlimit = '1') then nxt_state <= clr_cnt2;
                    else nxt_state <= idle;
                   end if; 
                  
  when clr_cnt2 => nxt_state <= T3st;
   
  when T3st     => if (signal_in_down = '1') then nxt_state <= check_T3; 
                    else nxt_state <= T3st;
                   end if;

  when check_T3 => if (T3inlimit = '1') then nxt_state <= found_seq;
                    else nxt_state <= idle;
                   end if; 

  when found_seq => nxt_state <= idle;
  
  when ignore    => if (signal_in_down = '1') then nxt_state <= idle;
  					 else nxt_state <= ignore;
  					end if;
  
  when others    => nxt_state <= idle;
 end case;
end process;

-- resetarea numaratoarelor
sync_counter_1 	<= '1' when (pst_state = idle) or (pst_state = clr_cnt1) else '0';
sync_counter_2 	<= '1' when (pst_state = idle) or (pst_state = clr_cnt2) else '0';
-- pornirea numaratoarelor
enable_counter_1  <= '1' when (pst_state = T1st) or (pst_state = check_T2) or (pst_state = clr_cnt2) or (pst_state = T3st)   else '0';
enable_counter_2  <= '1' when (pst_state = T1st) or (pst_state = check_T1) or (pst_state = clr_cnt1) or (pst_state = T2st) else '0';

sequence_found  <= '1' when (pst_state = found_seq) else '0';

end rtl_tx;