tcc_cdma_tb.v

来自「full testbench design including random 」· Verilog 代码 · 共 38 行

/**************************************/
// Highland Communications Technologies
// 225 Bowen Road, Fort Erie
// Ontario, Canada L2A 2Y6
// www.highlandcomm.com
// Copyright 20004
/**************************************/
// test fixture for 3GPP2(CDMA-2000) TCC

module tcc_cdma_tb (
	rst, clk, code_rate, early_term, 
	num_iters_in, snr, data_length, 
	start_encoder, start_decoder,
	encoder_out_ready, decoder_out_ready,
	num_iters_out, sig_value, noise_value,
	received_value, sig_pwr, noise_pwr,
	num_data, num_err, num_err1, err_sig,
	err_sig1);

  input rst, clk, early_term;
  input [1 : 0] code_rate;
  input [3 : 0] num_iters_in;
  input [7 : 0] snr;
  input [12 : 0] data_length;

  output start_encoder, start_decoder;
  output encoder_out_ready, decoder_out_ready;
  output [3 : 0] num_iters_out;
  output [15 : 0] sig_value;
  output [15 : 0] noise_value;
  output [3 : 0] received_value;
  output [15 : 0] sig_pwr;
  output [15 : 0] noise_pwr; 
  output [39 : 0] num_data;
  output [39 : 0] num_err;
  output [39 : 0] num_err1;
  output err_sig, err_sig1;
endmodule