mult2.vhd

来自「this is the multiplier 2 module for the 」· VHDL 代码 · 共 53 行

---------------------------------------------------------------------------------------------------
--
-- Title       : mult2
-- Design      : design2
-- Author      : aks
-- Company     : home
--
---------------------------------------------------------------------------------------------------
--
-- File        : mult2.vhd
-- Generated   : Mon Mar  9 12:13:56 2009
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description : 
--
---------------------------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {mult2} architecture {mult2}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity gf1 is
	port(
	fb:in bit_vector(0 to 2);
	pd:out bit_vector(0 to 2)
	);
end entity;
architecture gf1 of gf1 is	


begin 
	process(fb)	
	begin
	case fb is
		when "100"=>pd<="110";
		when "010"=>pd<="011";
		when "001"=>pd<="111";
		when "110"=>pd<="101";
		when "011"=>pd<="100";
		when "111"=>pd<="010";
		when "101"=>pd<="001";
		when others=>pd<="000";
		
	end case;  
	end process;
end gf1;