rsenc.vhd

this is the code for reed solomon encoder of type 7,3. this is the main module program.

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--
-- Title       : rsenc
-- Design      : design2
-- Author      : aks
-- Company     : home
--
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--
-- File        : rsenc.vhd
-- Generated   : Mon Mar  9 09:38:27 2009
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {rsenc} architecture {rsenc}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity rsenc is
	 port(
		 clk : in STD_LOGIC;
		 reset : in STD_LOGIC;
		 din : inout bit_vector(0 to 2);
		 dout : inout bit_vector(0 to 2)
	     );
end rsenc;

--}} End of automatically maintained section

architecture rsenc of rsenc is

signal fdl:bit_vector(0 to 2);

type prod is array(0 to 3) of bit_vector(0 to 2);  

 type reg is array(0 to 3) of bit_vector(0 to 2);	
signal reg1:reg;	
  


signal prd:prod;  
  constant n:integer:=7;
constant k:integer:=3;
constant m:integer:=3;

component gf0
	port(fb: in bit_vector(0 to 2);
			pd: out bit_vector(0 to 2));
end component;
component gf1
	port(fb:in bit_vector(0 to 2);
		pd:out bit_vector(0 to 2));
end component;
component gf2
	port(fb:in bit_vector(0 to 2);
			pd:out bit_vector(0 to 2));
end component;
component gf3
	port(fb:in bit_vector(0 to 2);
			pd:out bit_vector(0 to 2));
end component;
begin
	





process(din)  


begin
	fdl<=reg1(3) xor din;
end process;	

c0:gf0 port map (fdl,prd(0));
c1:gf1 port map (fdl,prd(1));
c2:gf2 port map (fdl,prd(2));
c3:gf3 port map (fdl,prd(3)); 

process(clk) 
variable mode:bit;
variable cnt:integer range 0 to 7;	
begin
	if (reset='1') then reg1(0)<="000";
	elsif (clk'event and clk='1') then
		if(cnt=0) then mode:='1';
		elsif(cnt=k) then mode:='0';
		elsif(cnt=n-m)then mode:='1';
			cnt:=0;
		end if;
		cnt:=cnt+1;
		end if;

if(mode='1') then
	reg1(3)<=reg1(2) xor prd(3);
	reg1(2)<=reg1(1) xor prd(2);
	reg1(1)<=reg1(0) xor prd(1);
	reg1(0)<=prd(0);
	dout<=din;

elsif(mode='0') then
	for i in 0 to 2 loop 
		
		dout<=reg1(3);
		reg1(3)<=reg1(2-i);
		reg1(2-i)<="000";
	end loop; 
end if;


end process;  

end rsenc;