📄 mc8051_p.vhd
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IC_MOVC_A_ATDPTR,
IC_MOVC_A_ATPC,
IC_MOVX_A_ATRI,
IC_MOVX_A_ATDPTR,
IC_MOVX_ATRI_A,
IC_MOVX_ATDPTR_A,
IC_MOV_C_BIT,
IC_MOV_BIT_C,
IC_MOV_DPTR_DATA,
IC_MUL_AB,
IC_NOP,
IC_ORL_A_RR,
IC_ORL_A_D,
IC_ORL_A_ATRI,
IC_ORL_A_DATA,
IC_ORL_D_A,
IC_ORL_D_DATA,
IC_ORL_C_BIT,
IC_ORL_C_NBIT,
IC_POP,
IC_PUSH,
IC_RET,
IC_RETI,
IC_RL_A,
IC_RLC_A,
IC_RR_A,
IC_RRC_A,
IC_SETB_C,
IC_SETB_BIT,
IC_SJMP,
IC_SUBB_A_RR,
IC_SUBB_A_D,
IC_SUBB_A_ATRI,
IC_SUBB_A_DATA,
IC_SWAP_A,
IC_XCH_A_RR,
IC_XCH_A_D,
IC_XCH_A_ATRI,
IC_XCHD_A_ATRI,
IC_XRL_A_RR,
IC_XRL_A_D,
IC_XRL_A_ATRI,
IC_XRL_A_DATA,
IC_XRL_D_A,
IC_XRL_D_DATA);
type t_tmr_lv is array(C_IMPL_N_TMR-1 downto 0) of
std_logic_vector(7 downto 0);
type t_tmr_us is array(C_IMPL_N_TMR-1 downto 0) of unsigned(7 downto 0);
type t_tmr_us2 is array(C_IMPL_N_TMR-1 downto 0) of unsigned(1 downto 0);
type t_tmr_l is array(C_IMPL_N_TMR-1 downto 0) of std_logic;
type t_siu_lv is array(C_IMPL_N_SIU-1 downto 0) of
std_logic_vector(7 downto 0);
type t_siu_us is array(C_IMPL_N_SIU-1 downto 0) of unsigned(7 downto 0);
type t_siu_l is array(C_IMPL_N_SIU-1 downto 0) of std_logic;
type t_ext_l is array(C_IMPL_N_EXT-1 downto 0) of std_logic;
component addsub_cy
generic (DWIDTH : integer);
port (opa_i : in std_logic_vector(DWIDTH-1 downto 0);
opb_i : in std_logic_vector(DWIDTH-1 downto 0);
addsub_i : in std_logic;
cy_i : in std_logic;
cy_o : out std_logic;
rslt_o : out std_logic_vector(DWIDTH-1 downto 0));
end component;
component addsub_ovcy
generic (DWIDTH : integer);
port (opa_i : in std_logic_vector(DWIDTH-1 downto 0);
opb_i : in std_logic_vector(DWIDTH-1 downto 0);
addsub_i : in std_logic;
cy_i : in std_logic;
cy_o : out std_logic;
ov_o : out std_logic;
rslt_o : out std_logic_vector(DWIDTH-1 downto 0));
end component;
component addsub_core
generic (DWIDTH : integer);
port (opa_i : in std_logic_vector(DWIDTH-1 downto 0);
opb_i : in std_logic_vector(DWIDTH-1 downto 0);
addsub_i : in std_logic;
cy_i : in std_logic;
cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
ov_o : out std_logic;
rslt_o : out std_logic_vector(DWIDTH-1 downto 0));
end component;
component alucore
generic (DWIDTH : integer);
port (op_a_i : in std_logic_vector(DWIDTH-1 downto 0);
op_b_i : in std_logic_vector(DWIDTH-1 downto 0);
alu_cmd_i : in std_logic_vector(3 downto 0);
cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);
cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
result_o : out std_logic_vector(DWIDTH-1 downto 0));
end component;
component comb_divider
generic (
DWIDTH : integer);
port (
dvdnd_i : in std_logic_vector(DWIDTH-1 downto 0);
dvsor_i : in std_logic_vector(DWIDTH-1 downto 0);
qutnt_o : out std_logic_vector(DWIDTH-1 downto 0);
rmndr_o : out std_logic_vector(DWIDTH-1 downto 0));
end component;
component comb_mltplr
generic (
DWIDTH : integer);
port (
mltplcnd_i : in std_logic_vector(DWIDTH-1 downto 0);
mltplctr_i : in std_logic_vector(DWIDTH-1 downto 0);
product_o : out std_logic_vector((DWIDTH*2)-1 downto 0));
end component;
component dcml_adjust
generic (
DWIDTH : integer);
port (
data_i : in std_logic_vector(DWIDTH-1 downto 0);
cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);
data_o : out std_logic_vector(DWIDTH-1 downto 0);
cy_o : out std_logic);
end component;
component alumux
generic (DWIDTH : integer);
port (rom_data_i : in std_logic_vector(DWIDTH-1 downto 0);
ram_data_i : in std_logic_vector(DWIDTH-1 downto 0);
acc_i : in std_logic_vector(DWIDTH-1 downto 0);
cmd_i : in std_logic_vector(5 downto 0);
cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);
ov_i : in std_logic;
cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
ov_o : out std_logic;
result_a_o : out std_logic_vector(DWIDTH-1 downto 0);
result_b_o : out std_logic_vector(DWIDTH-1 downto 0);
result_i : in std_logic_vector(DWIDTH-1 downto 0);
new_cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);
addsub_rslt_i : in std_logic_vector(DWIDTH-1 downto 0);
addsub_cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);
addsub_ov_i : in std_logic;
op_a_o : out std_logic_vector(DWIDTH-1 downto 0);
op_b_o : out std_logic_vector(DWIDTH-1 downto 0);
alu_cmd_o : out std_logic_vector(3 downto 0);
opa_o : out std_logic_vector(DWIDTH-1 downto 0);
opb_o : out std_logic_vector(DWIDTH-1 downto 0);
addsub_o : out std_logic;
addsub_cy_o : out std_logic;
dvdnd_o : out std_logic_vector(DWIDTH-1 downto 0);
dvsor_o : out std_logic_vector(DWIDTH-1 downto 0);
qutnt_i : in std_logic_vector(DWIDTH-1 downto 0);
rmndr_i : in std_logic_vector(DWIDTH-1 downto 0);
mltplcnd_o : out std_logic_vector(DWIDTH-1 downto 0);
mltplctr_o : out std_logic_vector(DWIDTH-1 downto 0);
product_i : in std_logic_vector((DWIDTH*2)-1 downto 0);
dcml_data_o : out std_logic_vector(DWIDTH-1 downto 0);
dcml_data_i : in std_logic_vector(DWIDTH-1 downto 0);
dcml_cy_i : in std_logic);
end component;
component mc8051_alu
generic (
DWIDTH : integer);
port (
rom_data_i : in std_logic_vector(DWIDTH-1 downto 0);
ram_data_i : in std_logic_vector(DWIDTH-1 downto 0);
acc_i : in std_logic_vector(DWIDTH-1 downto 0);
cmd_i : in std_logic_vector(5 downto 0);
cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);
ov_i : in std_logic;
new_cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
new_ov_o : out std_logic;
result_a_o : out std_logic_vector(DWIDTH-1 downto 0);
result_b_o : out std_logic_vector(DWIDTH-1 downto 0));
end component;
component mc8051_siu
port (clk : in std_logic;
reset : in std_logic;
tf_i : in std_logic;
trans_i : in std_logic;
rxd_i : in std_logic;
scon_i : in std_logic_vector(5 downto 0);
sbuf_i : in std_logic_vector(7 downto 0);
smod_i : in std_logic;
sbuf_o : out std_logic_vector(7 downto 0);
scon_o : out std_logic_vector(2 downto 0);
rxdwr_o : out std_logic;
rxd_o : out std_logic;
txd_o : out std_logic);
end component;
component mc8051_tmrctr
port (clk : in std_logic;
reset : in std_logic;
int0_i : in std_logic;
int1_i : in std_logic;
t0_i : in std_logic;
t1_i : in std_logic;
tmod_i : in std_logic_vector(7 downto 0);
tcon_tr0_i : in std_logic;
tcon_tr1_i : in std_logic;
reload_i : in std_logic_vector(7 downto 0);
wt_en_i : in std_logic;
wt_i : in std_logic_vector(1 downto 0);
th0_o : out std_logic_vector(7 downto 0);
tl0_o : out std_logic_vector(7 downto 0);
th1_o : out std_logic_vector(7 downto 0);
tl1_o : out std_logic_vector(7 downto 0);
tf0_o : out std_logic;
tf1_o : out std_logic);
end component;
component control_fsm
port ( state_i : in t_state; -- actual state
help_i : in std_logic_vector (7 downto 0); -- general help-reg
bit_data_i : in std_logic; -- bitdata from regs
aludata_i : in std_logic_vector (7 downto 0); -- ALU result
command_i : in std_logic_vector (7 downto 0); -- actual command
inthigh_i : in std_logic; -- high priority int is running
intlow_i : in std_logic; -- low priority int is running
intpre_i : in std_logic; -- an interrupt must start
intpre2_i : in std_logic; -- prepare for interrupt
intblock_i : in std_logic; -- interrupt delay at RETI, IE, IP
ti_i : in std_logic;
ri_i : in std_logic;
ie0_i : in std_logic;
ie1_i : in std_logic;
tf0_i : in std_logic;
tf1_i : in std_logic;
acc : in std_logic_vector(7 downto 0);
psw : in std_logic_vector(7 downto 0);
ie : in std_logic_vector(7 downto 0);
ip : in std_logic_vector(7 downto 0);
alu_cmd_o : out std_logic_vector (5 downto 0); -- ALU code
pc_inc_en_o : out std_logic_vector (3 downto 0);
nextstate_o : out t_state;
adr_mux_o : out std_logic_vector (3 downto 0);
adrx_mux_o : out std_logic_vector (1 downto 0);
wrx_mux_o : out std_logic;
data_mux_o : out std_logic_vector (3 downto 0);
bdata_mux_o : out std_logic_vector (3 downto 0);
regs_wr_en_o : out std_logic_vector (2 downto 0);
help_en_o : out std_logic_vector (3 downto 0);
help16_en_o : out std_logic_vector (1 downto 0);
helpb_en_o : out std_logic;
inthigh_en_o : out std_logic;
intlow_en_o : out std_logic;
intpre2_en_o : out std_logic;
inthigh_d_o : out std_logic;
intlow_d_o : out std_logic;
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