fet140_dma_07.s43

MSP430的汇编开发例子

;******************************************************************************
;   MSP-FET430P140 Demo - DMA0/1, Rpt'd Blk to DAC12_0/1, Sin/Cos, TACCR1, XT2
;
;   Description: DMA0 and DMA1 are used to transfer a sine and cos look-up table
;   word-by-word as a repeating block to DAC12_0 and DAC12_1. The effect is sine
;   and cos wave outputs. Timer_A operates in upmode with TACCR1 loading
;   DAC12_0 amd DAC12_1 on rising edge and DAC12_OIFG triggering next DMA0
;   DMA1 transfers. DAC12_0 and DAC12_1 are grouped for gitter-free operation.
;   ACLK= n/a, MCLK= SMCLK= TACLK= XT2= 8MHz
;   //* An external 8MHz XTAL on X2IN X2OUT is required for XT2CLK *//	
;   //* MSP430F169 Device Required *//
;
;                MSP430F169
;             -----------------
;         /|\|            XT2IN|-
;          | |                 | 8MHz
;          --|RST        XT2OUT|-
;            |                 |
;            |        DAC0/P6.6|--> ~ 10kHz sine wave
;            |        DAC1/P6.7|--> ~ 10kHz cos wave
;
;
;   M. Buccini
;   Texas Instruments Inc.
;   Feb 2005
;   Built with IAR Embedded Workbench Version: 3.21A
;******************************************************************************
#include  <msp430x16x.h>
;------------------------------------------------------------------------------
            ORG     01100h                  ; Progam Start
;------------------------------------------------------------------------------
RESET       mov.w   #0A00h,SP               ; Initialize stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop watchdog timer
SetupBC     bic.b   #XT2OFF,&BCSCTL1        ; XT2on
SetupOsc    bic.b   #OFIFG,&IFG1            ; Clear OSC fault flag
            mov.w   #0FFh,R15               ; R15 = Delay
SetupOsc1   dec.w   R15                     ; Additional delay to ensure start
            jnz     SetupOsc1               ;
            bit.b   #OFIFG,&IFG1            ; OSC fault flag set?
            jnz     SetupOsc                ; OSC Fault, clear flag again
            bis.b   #SELM_2+SELS,BCSCTL2    ; MCLK = SMCLK = XT2

SetupADC12  mov.w   #REF2_5V+REFON,&ADC12CTL0 ; Internal 2.5V ref
            mov.w   #13600,&TACCR0          ; Delay to allow Ref to settle
            bis.w   #CCIE,&TACCTL0          ; Compare-mode interrupt.
            mov.w   #TACLR+MC_1+TASSEL_2,&TACTL; up mode, SMCLK
            bis.w   #LPM0+GIE,SR            ; Enter LPM0, enable interrupts
            bic.w   #CCIE,&TACCTL0          ; Disable timer interrupt
            dint                            ; Disable Interrupts
SetupDMAx   mov.w   #DMA0TSEL_5+DMA1TSEL_5,&DMACTL0 ; DAC12IFG triggers
            mov.w   #Sin_tab,&DMA0SA        ; Source block address
            mov.w   #DAC12_0DAT,&DMA0DA     ; Destination single address
            mov.w   #020h,&DMA0SZ           ; Block size
            mov.w   #DMADT_4+DMASRCINCR_3+DMAEN,&DMA0CTL; Rpt, inc src, word-word
            mov.w   #Cos_tab,&DMA1SA        ; Source block address
            mov.w   #DAC12_1DAT,&DMA1DA     ; Destination single address
            mov.w   #020h,&DMA1SZ           ; Block size
            mov.w   #DMADT_4+DMASRCINCR_3+DMAEN,&DMA1CTL; Rpt, inc src, word-word
SetupDAC12x mov.w   #DAC12LSEL_2+DAC12IR+DAC12AMP_5+DAC12IFG+DAC12ENC+DAC12GRP,&DAC12_0CTL
            mov.w   #DAC12LSEL_2+DAC12IR+DAC12AMP_5+DAC12IFG+DAC12ENC,&DAC12_1CTL
SetupC1     mov.w   #OUTMOD_3,&CCTL1        ; CCR1 set/reset
            mov.w   #01,&CCR1               ; CCR1 PWM Duty Cycle	
SetupC0     mov.w   #025-1,&CCR0            ; Clock period of CCR0
SetupTA     mov.w   #TASSEL_2+MC_1,&TACTL   ; SMCLK, contmode
                                            ;
Mainloop    bis.b   #CPUOFF,SR              ; Enter LPM0
            nop                             ; Needed only for debugger
                                            ;
;------------------------------------------------------------------------------
TAX_ISR;    Common ISR for CCR0-4 and overflow
;------------------------------------------------------------------------------
            add.w   &TAIV,PC                ; Add TA interrupt offset to PC
            jmp     TACCR0_ISR              ; CCR0
            reti                            ; CCR1
            reti                            ; CCR2
            reti                            ; CCR3
            reti                            ; CCR4
TA_over     reti                            ; Timer_A overflow

TACCR0_ISR  clr     &TACTL                  ; clear Timer_A control registers
            bic     #LPM0,0(SP)             ; Exit LPMx, interrupts enabled
            reti                            ;
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
; 12-bit Sine Lookup table with 32 steps
;------------------------------------------------------------------------------
Sin_tab     DW 2048, 2447, 2831, 3185, 3495, 3750, 3939, 4056
            DW 4095, 4056, 3939, 3750, 3495, 3185, 2831, 2447
            DW 2048, 1648, 1264,  910,  600,  345,  156,   39
            DW    0,   39,  156,  345,  600,  910, 1264, 1648
;
;------------------------------------------------------------------------------
; 12-bit Cosine Lookup table with 32 steps
;------------------------------------------------------------------------------
Cos_tab     DW 1648, 1264,  910,  600,  345,  156,   39,    0
            DW   39,   56,  345,  600,  910, 1264, 1648, 2048
            DW 2447, 2831, 3185, 3495, 3750, 3939, 4056, 4095
            DW 4056, 3939, 3750, 3495, 3185, 2831, 2447, 2048

;------------------------------------------------------------------------------
;           Interrupt Vectors
;------------------------------------------------------------------------------
             ORG     0FFFEh                  ; POR, ext. Reset, Watchdog, Flash
             DW      RESET                   ;
             ORG     0FFECh                  ; Timer_A0 Vector
             DW      TAX_ISR                 ;
             END