usb.c

源代码

					}
					if((descSetup.bIndexL & 0x8f) == 0x04){          // OUT Endpoint 3	// by J.I modified(8/22) Endpoint 3-> Endpoint 4
						StatusGet.Endpoint4= 0;      
					}
				}
				break;

			default:
				break;
			}
			CLR_EP0_OUTPKTRDY_DATAEND();
			ep0State=EP0_STATE_INIT;
			break;

		case GET_CONFIGURATION:
			CLR_EP0_OUT_PKT_RDY();
			ep0State=EP0_CONFIG_SET;
			break;

		case GET_INTERFACE:
			CLR_EP0_OUT_PKT_RDY();
			ep0State=EP0_INTERFACE_GET;
			break;

		case GET_STATUS:
			switch(descSetup.bmRequestType)
			{
			case  (0x80):
				CLR_EP0_OUT_PKT_RDY();
				StatusGet.Device=((U8)Rwuen<<1)|(U8)Selfpwr;
				ep0State=EP0_GET_STATUS0;
				break;

			case  (0x81):
				CLR_EP0_OUT_PKT_RDY();
				StatusGet.Interface=0;
				ep0State=EP0_GET_STATUS1;
				break;

			case  (0x82):
				CLR_EP0_OUT_PKT_RDY();
				if((descSetup.bIndexL & 0x7f) == 0x00){
					ep0State=EP0_GET_STATUS2;
				}
				if((descSetup.bIndexL & 0x8f) == 0x81){
					ep0State=EP0_GET_STATUS3;
				}
				if((descSetup.bIndexL & 0x8f) == 0x04){		// OUT Endpoint 3	// by J.I modified(8/22) Endpoint 3-> Endpoint 4
					ep0State=EP0_GET_STATUS4;
				}
				break;

			default:
				break;
    	  	}
    	  	break;

		case SET_DESCRIPTOR:
			CLR_EP0_OUTPKTRDY_DATAEND();
			ep0State=EP0_STATE_INIT;
			break;

		case SET_FEATURE:
			switch (descSetup.bmRequestType)
			{
			case DEVICE_RECIPIENT:
				if (descSetup.bValueL == 1)
					Rwuen = TRUE;
				break;

			case ENDPOINT_RECIPIENT:
				if (descSetup.bValueL == 0)
				{
					if((descSetup.bIndexL & 0x7f) == 0x00){
						StatusGet.Endpoint0= 1;
					}
					if((descSetup.bIndexL & 0x8f) == 0x81){
						StatusGet.Endpoint1= 1;
					}
					if((descSetup.bIndexL & 0x8f) == 0x04){		// by J.I modified(8/22) Endpoint3-> Endpoint4
						StatusGet.Endpoint4= 1;
					}
				}
				break;
			default:
			break;
			}
			CLR_EP0_OUTPKTRDY_DATAEND();
			ep0State=EP0_STATE_INIT;
			break;

		case SET_INTERFACE:
			InterfaceGet.AlternateSetting= descSetup.bValueL;
			CLR_EP0_OUTPKTRDY_DATAEND(); 
			ep0State=EP0_STATE_INIT;
			break;

		case SYNCH_FRAME:
			ep0State=EP0_STATE_INIT;
			break;

    	  //////////////////////////////////////////////////////////////

		default:
			EdbgOutputDebugString("[UE:SETUP=%x]\r\n",descSetup.bRequest);
			CLR_EP0_OUTPKTRDY_DATAEND(); //Because of no data control transfers.
			ep0State=EP0_STATE_INIT;
			break;
		}
	}

	switch(ep0State)
	{
	case EP0_STATE_INIT:
		break; 

	//=== GET_DESCRIPTOR:DEVICE ===
	case EP0_STATE_GD_DEV_0:
		WrPktEp0((U8 *)&descDev+0,8); //EP0_PKT_SIZE
		SET_EP0_IN_PKT_RDY();
		ep0State=EP0_STATE_GD_DEV_1;
		break;

	case EP0_STATE_GD_DEV_1:
		WrPktEp0((U8 *)&descDev+0x8,8); 
		SET_EP0_IN_PKT_RDY();
		ep0State=EP0_STATE_GD_DEV_2;
		break;

	case EP0_STATE_GD_DEV_2:
		WrPktEp0((U8 *)&descDev+0x10,2);   //8+8+2=0x12
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;
		break;

	//=== GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 ===
	//Windows98 gets these 4 descriptors all together by issuing only a request.
	//Windows2000 gets each descriptor seperately.
	case EP0_STATE_GD_CFG_0:
		WrPktEp0((U8 *)&descConf+0,8); //EP0_PKT_SIZE
		SET_EP0_IN_PKT_RDY();
		ep0State=EP0_STATE_GD_CFG_1;
		break;

	case EP0_STATE_GD_CFG_1:
		WrPktEp0((U8 *)&descConf+8,1); 
		WrPktEp0((U8 *)&descIf+0,7); 
		SET_EP0_IN_PKT_RDY();
		ep0State=EP0_STATE_GD_CFG_2;
		break;

	case EP0_STATE_GD_CFG_2:
		WrPktEp0((U8 *)&descIf+7,2); 
		WrPktEp0((U8 *)&descEndpt0+0,6); 
		SET_EP0_IN_PKT_RDY();
		ep0State=EP0_STATE_GD_CFG_3;
		break;

	case EP0_STATE_GD_CFG_3:
		WrPktEp0((U8 *)&descEndpt0+6,1); 
		WrPktEp0((U8 *)&descEndpt1+0,7); 
		SET_EP0_IN_PKT_RDY();
		ep0State=EP0_STATE_GD_CFG_4;            
		break;

	case EP0_STATE_GD_CFG_4:
		 //zero length data packit 
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;            
		break;

	//=== GET_DESCRIPTOR:CONFIGURATION ONLY===
	case EP0_STATE_GD_CFG_ONLY_0:
		WrPktEp0((U8 *)&descConf+0,8); //EP0_PKT_SIZE
		SET_EP0_IN_PKT_RDY();
		ep0State=EP0_STATE_GD_CFG_ONLY_1;
		break;
    
	case EP0_STATE_GD_CFG_ONLY_1:
		WrPktEp0((U8 *)&descConf+8,1); 
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;            
		break;

	//=== GET_DESCRIPTOR:INTERFACE ONLY===
	case EP0_STATE_GD_IF_ONLY_0:
		EdbgOutputDebugString("[GDI0]\r\n");
		WrPktEp0((U8 *)&descIf+0,8); 
		SET_EP0_IN_PKT_RDY();
		ep0State=EP0_STATE_GD_IF_ONLY_1;
		break;

	case EP0_STATE_GD_IF_ONLY_1:
		EdbgOutputDebugString("[GDI1]\r\n");
		WrPktEp0((U8 *)&descIf+8,1); 
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;            
		break;

	//=== GET_DESCRIPTOR:ENDPOINT 0 ONLY===
	case EP0_STATE_GD_EP0_ONLY_0:
		EdbgOutputDebugString("[GDE00]\r\n");
		WrPktEp0((U8 *)&descEndpt0+0,7); 
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;            
		break;
            
	//=== GET_DESCRIPTOR:ENDPOINT 1 ONLY===
	case EP0_STATE_GD_EP1_ONLY_0:
		EdbgOutputDebugString("[GDE10]\r\n");
		WrPktEp0((U8 *)&descEndpt1+0,7); 
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;            
		break;
            
////////////////////////////////////////////

	case EP0_INTERFACE_GET:
		WrPktEp0((U8 *)&InterfaceGet+0,1);
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

 
	//=== GET_DESCRIPTOR:STRING ===
	case EP0_STATE_GD_STR_I0:
		WrPktEp0((U8 *)descStr0, 4 );  
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;     
		ep0SubState=0;
		break;

	case EP0_STATE_GD_STR_I1:
		if( (ep0SubState*EP0_PKT_SIZE+EP0_PKT_SIZE)<sizeof(descStr1) )
		{
			WrPktEp0((U8 *)descStr1+(ep0SubState*EP0_PKT_SIZE),EP0_PKT_SIZE); 
			SET_EP0_IN_PKT_RDY();
			ep0State=EP0_STATE_GD_STR_I1;
			ep0SubState++;
		}
		else
		{
			WrPktEp0((U8 *)descStr1+(ep0SubState*EP0_PKT_SIZE),
			sizeof(descStr1)-(ep0SubState*EP0_PKT_SIZE)); 
			SET_EP0_INPKTRDY_DATAEND();
			ep0State=EP0_STATE_INIT;     
			ep0SubState=0;
		}
		break;

	case EP0_STATE_GD_STR_I2:
		if( (ep0SubState*EP0_PKT_SIZE+EP0_PKT_SIZE)<sizeof(descStr2) )
		{
			WrPktEp0((U8 *)descStr2+(ep0SubState*EP0_PKT_SIZE),EP0_PKT_SIZE); 
			SET_EP0_IN_PKT_RDY();
			ep0State=EP0_STATE_GD_STR_I2;
			ep0SubState++;
		}
		else
		{
			WrPktEp0((U8 *)descStr2+(ep0SubState*EP0_PKT_SIZE),
			sizeof(descStr2)-(ep0SubState*EP0_PKT_SIZE)); 
			SET_EP0_INPKTRDY_DATAEND();
			ep0State=EP0_STATE_INIT;     
			ep0SubState=0;
		}
		break;

	case EP0_CONFIG_SET:
		WrPktEp0((U8 *)&ConfigSet+0,1); 
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	case EP0_GET_STATUS0:
		WrPktEp0((U8 *)&StatusGet+0,1);
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	case EP0_GET_STATUS1:
		WrPktEp0((U8 *)&StatusGet+1,1);
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	case EP0_GET_STATUS2:
		WrPktEp0((U8 *)&StatusGet+2,1);
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	case EP0_GET_STATUS3:
		WrPktEp0((U8 *)&StatusGet+3,1);
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	case EP0_GET_STATUS4:
		WrPktEp0((U8 *)&StatusGet+4,1);
		SET_EP0_INPKTRDY_DATAEND();
		ep0State=EP0_STATE_INIT;      
		break;

	default:
//		DbgPrintf("UE:G?D");
		EdbgOutputDebugString("[UE:G?D]\r\n");
		break;
	}
}

void ReconfigUsbd(void)
{
// *** End point information ***
//   EP0: control
//   EP1: bulk in end point
//   EP2: not used
//   EP3: bulk out end point --> not used	by J.I modifed(8/22)
//   EP4: not used --> bulk out end point   by J.I modified(8/22)
    
	// disable suspend mode by J.I comment added(8/25)
	pUSBCtrlAddr->PMR.sus_en = 0;
	pUSBCtrlAddr->PMR.sus_mo = 0;
	pUSBCtrlAddr->PMR.mcu_res = 0;
	pUSBCtrlAddr->PMR.usb_re = 0;
	pUSBCtrlAddr->PMR.iso_up = 0;

	// EndPoint 0 Setup by J.I comment added(8/25)
	pUSBCtrlAddr->INDEX.index = 0;
	pUSBCtrlAddr->MAXP.maxp = 0x01;	//EP0 max packit size = 8 
	pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
	pUSBCtrlAddr->EP0ICSR1.sse_ = 1;
	//EP0:clear OUT_PKT_RDY & SETUP_END

	pUSBCtrlAddr->INDEX.index = 1;
	pUSBCtrlAddr->MAXP.maxp = 0x08;	//EP1 max packit size = 64 
	pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
	pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
	pUSBCtrlAddr->ICSR2.mode_in = 1;
	pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;
	pUSBCtrlAddr->ICSR2.iso = 0;
	pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
	pUSBCtrlAddr->OCSR2.iso = 0;
	pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;

	pUSBCtrlAddr->INDEX.index = 2;
	pUSBCtrlAddr->MAXP.maxp = 0x08;	//EP2 max packit size = 64 
	pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
	pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
	pUSBCtrlAddr->ICSR2.mode_in = 1;
	pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;
	pUSBCtrlAddr->ICSR2.iso = 0;
	pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
	pUSBCtrlAddr->OCSR2.iso = 0;
	pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;

	pUSBCtrlAddr->INDEX.index = 3;
	pUSBCtrlAddr->MAXP.maxp = 0x08;	//EP3 max packit size = 64 
	pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
	pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
	pUSBCtrlAddr->ICSR2.mode_in = 0;		
	pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;	// dma interrupt disable by J.I modifed(8/22)
	pUSBCtrlAddr->ICSR2.iso = 0;
	pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
	//clear OUT_PKT_RDY, data_toggle_bit.
	//The data toggle bit should be cleared when initialization.
	pUSBCtrlAddr->OCSR2.iso = 0;
	pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;

	pUSBCtrlAddr->INDEX.index = 4;
	pUSBCtrlAddr->MAXP.maxp = 0x08;	//EP4 max packit size = 64 
	pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
	pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
	pUSBCtrlAddr->ICSR2.mode_in = 0;			// Endpoint Direction is OUT (RX),  Flow is Host to 24X0
	pUSBCtrlAddr->ICSR2.in_dma_int_en = 0;	// dma interrupt enable by J.I modifed(8/22)
	pUSBCtrlAddr->ICSR2.iso = 0;
	pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
	//clear OUT_PKT_RDY, data_toggle_bit.
	//The data toggle bit should be cleared when initialization.
	pUSBCtrlAddr->OCSR2.iso = 0;
	pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;

	pUSBCtrlAddr->EIR.ep0_int=1;
	pUSBCtrlAddr->EIR.ep1_int=1;
	pUSBCtrlAddr->EIR.ep2_int=1;
	pUSBCtrlAddr->EIR.ep3_int=1;
	pUSBCtrlAddr->EIR.ep4_int=1;
	pUSBCtrlAddr->UIR.reset_int = 1;
	pUSBCtrlAddr->UIR.sus_int = 1;
	pUSBCtrlAddr->UIR.resume_int = 1;

	//Clear all usbd pending bits

	//EP0,1,4 & reset interrupt are enabled	// by J.I modifed(8/22) EP3->EP4
	pUSBCtrlAddr->EIER.ep0_int_en = 1;
	pUSBCtrlAddr->EIER.ep1_int_en = 1;
	pUSBCtrlAddr->EIER.ep4_int_en = 1;	// by J.I modifed(8/22) EP3->EP4

	pUSBCtrlAddr->UIER.reset_int_en = 1;
	ep0State=EP0_STATE_INIT;

}

#define    BIT_ALLMSK       (0xffffffff)
#define    BIT_USBD         (0x1<<25)
//#define    BIT_DMA2         (0x1<<19)
#define    BIT_DMA3         (0x1<<20)

/// USB & DMA isr initialization
void Isr_Init(void)
{
    volatile S3C2440A_INTR_REG *s2440INT = (S3C2440A_INTR_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_INTR, FALSE);

	s2440INT->INTMOD=0x0;	  // All=IRQ mode
	s2440INT->INTMSK=BIT_ALLMSK;	  // All interrupt is masked.

//	EdbgOutputDebugString("INFO: (unsigned)IsrUsbd : 0x%x\r\n", (unsigned)IsrUsbd);
//	EdbgOutputDebugString("INFO: (unsigned)IsrHandler : 0x%x\r\n", (unsigned)IsrHandler);

	// make value to assemble code "b IsrHandler"
	pISR =(unsigned)(0xEA000000)+(((unsigned)IsrHandler - (0x80000000 + 0x18 + 0x8) )>>2);

//	EdbgOutputDebugString("INFO: (unsigned)pISR : 0x%x\r\n", (unsigned)pISR);

	s2440INT->SRCPND  = BIT_USBD;
	if (s2440INT->INTPND & BIT_USBD) s2440INT->INTPND = BIT_USBD;
	s2440INT->INTMSK &= ~BIT_USBD;		// USB Interrupt enable.

	// by J.I modified(8/22) DMA2-->DMA3 ch
	s2440INT->SRCPND  = BIT_DMA3;
	if (s2440INT->INTPND & BIT_DMA3) s2440INT->INTPND = BIT_DMA3;
	s2440INT->INTMSK &= ~BIT_DMA3;		// DMA Interrupt enable.
}

void IsrUsbd(unsigned int val)
{
    U8 saveIndexReg=pUSBCtrlAddr->INDEX.index;