defbf561.h

u-boot1.3.0的原码,从配了网络驱动和FLASH的驱动,并该用ESC竟如

#define DMA1_8_CONFIG		0xFFC01E08	/* DMA1 Channel 8 Configuration register */
#define DMA1_8_NEXT_DESC_PTR	0xFFC01E00	/* DMA1 Channel 8 Next Descripter Ptr Reg */
#define DMA1_8_START_ADDR	0xFFC01E04	/* DMA1 Channel 8 Start Address */
#define DMA1_8_X_COUNT		0xFFC01E10	/* DMA1 Channel 8 Inner Loop Count */
#define DMA1_8_Y_COUNT		0xFFC01E18	/* DMA1 Channel 8 Outer Loop Count */
#define DMA1_8_X_MODIFY		0xFFC01E14	/* DMA1 Channel 8 Inner Loop Addr Increment */
#define DMA1_8_Y_MODIFY		0xFFC01E1C	/* DMA1 Channel 8 Outer Loop Addr Increment */
#define DMA1_8_CURR_DESC_PTR	0xFFC01E20	/* DMA1 Channel 8 Current Descriptor Pointer */
#define DMA1_8_CURR_ADDR	0xFFC01E24	/* DMA1 Channel 8 Current Address Pointer */
#define DMA1_8_CURR_X_COUNT	0xFFC01E30	/* DMA1 Channel 8 Current Inner Loop Count */
#define DMA1_8_CURR_Y_COUNT	0xFFC01E38	/* DMA1 Channel 8 Current Outer Loop Count */
#define DMA1_8_IRQ_STATUS	0xFFC01E28	/* DMA1 Channel 8 Interrupt Status Register */
#define DMA1_8_PERIPHERAL_MAP	0xFFC01E2C	/* DMA1 Channel 8 Peripheral Map Register */

#define DMA1_9_CONFIG		0xFFC01E48	/* DMA1 Channel 9 Configuration register */
#define DMA1_9_NEXT_DESC_PTR	0xFFC01E40	/* DMA1 Channel 9 Next Descripter Ptr Reg */
#define DMA1_9_START_ADDR	0xFFC01E44	/* DMA1 Channel 9 Start Address */
#define DMA1_9_X_COUNT		0xFFC01E50	/* DMA1 Channel 9 Inner Loop Count */
#define DMA1_9_Y_COUNT		0xFFC01E58	/* DMA1 Channel 9 Outer Loop Count */
#define DMA1_9_X_MODIFY		0xFFC01E54	/* DMA1 Channel 9 Inner Loop Addr Increment */
#define DMA1_9_Y_MODIFY		0xFFC01E5C	/* DMA1 Channel 9 Outer Loop Addr Increment */
#define DMA1_9_CURR_DESC_PTR	0xFFC01E60	/* DMA1 Channel 9 Current Descriptor Pointer */
#define DMA1_9_CURR_ADDR	0xFFC01E64	/* DMA1 Channel 9 Current Address Pointer */
#define DMA1_9_CURR_X_COUNT	0xFFC01E70	/* DMA1 Channel 9 Current Inner Loop Count */
#define DMA1_9_CURR_Y_COUNT	0xFFC01E78	/* DMA1 Channel 9 Current Outer Loop Count */
#define DMA1_9_IRQ_STATUS	0xFFC01E68	/* DMA1 Channel 9 Interrupt Status Register */
#define DMA1_9_PERIPHERAL_MAP	0xFFC01E6C	/* DMA1 Channel 9 Peripheral Map Register */

#define DMA1_10_CONFIG		0xFFC01E88	/* DMA1 Channel 10 Configuration register */
#define DMA1_10_NEXT_DESC_PTR	0xFFC01E80	/* DMA1 Channel 10 Next Descripter Ptr Reg */
#define DMA1_10_START_ADDR	0xFFC01E84	/* DMA1 Channel 10 Start Address */
#define DMA1_10_X_COUNT		0xFFC01E90	/* DMA1 Channel 10 Inner Loop Count */
#define DMA1_10_Y_COUNT		0xFFC01E98	/* DMA1 Channel 10 Outer Loop Count */
#define DMA1_10_X_MODIFY	0xFFC01E94	/* DMA1 Channel 10 Inner Loop Addr Increment */
#define DMA1_10_Y_MODIFY	0xFFC01E9C	/* DMA1 Channel 10 Outer Loop Addr Increment */
#define DMA1_10_CURR_DESC_PTR	0xFFC01EA0	/* DMA1 Channel 10 Current Descriptor Pointer */
#define DMA1_10_CURR_ADDR	0xFFC01EA4	/* DMA1 Channel 10 Current Address Pointer */
#define DMA1_10_CURR_X_COUNT	0xFFC01EB0	/* DMA1 Channel 10 Current Inner Loop Count */
#define DMA1_10_CURR_Y_COUNT	0xFFC01EB8	/* DMA1 Channel 10 Current Outer Loop Count */
#define DMA1_10_IRQ_STATUS	0xFFC01EA8	/* DMA1 Channel 10 Interrupt Status Register */
#define DMA1_10_PERIPHERAL_MAP	0xFFC01EAC	/* DMA1 Channel 10 Peripheral Map Register */

#define DMA1_11_CONFIG		0xFFC01EC8	/* DMA1 Channel 11 Configuration register */
#define DMA1_11_NEXT_DESC_PTR	0xFFC01EC0	/* DMA1 Channel 11 Next Descripter Ptr Reg */
#define DMA1_11_START_ADDR	0xFFC01EC4	/* DMA1 Channel 11 Start Address */
#define DMA1_11_X_COUNT		0xFFC01ED0	/* DMA1 Channel 11 Inner Loop Count */
#define DMA1_11_Y_COUNT		0xFFC01ED8	/* DMA1 Channel 11 Outer Loop Count */
#define DMA1_11_X_MODIFY	0xFFC01ED4	/* DMA1 Channel 11 Inner Loop Addr Increment */
#define DMA1_11_Y_MODIFY	0xFFC01EDC	/* DMA1 Channel 11 Outer Loop Addr Increment */
#define DMA1_11_CURR_DESC_PTR	0xFFC01EE0	/* DMA1 Channel 11 Current Descriptor Pointer */
#define DMA1_11_CURR_ADDR	0xFFC01EE4	/* DMA1 Channel 11 Current Address Pointer */
#define DMA1_11_CURR_X_COUNT	0xFFC01EF0	/* DMA1 Channel 11 Current Inner Loop Count */
#define DMA1_11_CURR_Y_COUNT	0xFFC01EF8	/* DMA1 Channel 11 Current Outer Loop Count */
#define DMA1_11_IRQ_STATUS	0xFFC01EE8	/* DMA1 Channel 11 Interrupt Status Register */
#define DMA1_11_PERIPHERAL_MAP	0xFFC01EEC	/* DMA1 Channel 11 Peripheral Map Register */

/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
#define MDMA1_D0_CONFIG		0xFFC01F08	/* MemDMA1 Stream 0 Destination Configuration */
#define MDMA1_D0_NEXT_DESC_PTR	0xFFC01F00	/* MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
#define MDMA1_D0_START_ADDR	0xFFC01F04	/* MemDMA1 Stream 0 Destination Start Address */
#define MDMA1_D0_X_COUNT	0xFFC01F10	/* MemDMA1 Stream 0 Destination Inner-Loop Count */
#define MDMA1_D0_Y_COUNT	0xFFC01F18	/* MemDMA1 Stream 0 Destination Outer-Loop Count */
#define MDMA1_D0_X_MODIFY	0xFFC01F14	/* MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
#define MDMA1_D0_Y_MODIFY	0xFFC01F1C	/* MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
#define MDMA1_D0_CURR_DESC_PTR	0xFFC01F20	/* MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
#define MDMA1_D0_CURR_ADDR	0xFFC01F24	/* MemDMA1 Stream 0 Destination Current Address */
#define MDMA1_D0_CURR_X_COUNT	0xFFC01F30	/* MemDMA1 Stream 0 Dest Current Inner-Loop Count */
#define MDMA1_D0_CURR_Y_COUNT	0xFFC01F38	/* MemDMA1 Stream 0 Dest Current Outer-Loop Count */
#define MDMA1_D0_IRQ_STATUS	0xFFC01F28	/* MemDMA1 Stream 0 Destination Interrupt/Status */
#define MDMA1_D0_PERIPHERAL_MAP	0xFFC01F2C	/* MemDMA1 Stream 0 Destination Peripheral Map */

#define MDMA1_S0_CONFIG		0xFFC01F48	/* MemDMA1 Stream 0 Source Configuration */
#define MDMA1_S0_NEXT_DESC_PTR	0xFFC01F40	/* MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
#define MDMA1_S0_START_ADDR	0xFFC01F44	/* MemDMA1 Stream 0 Source Start Address */
#define MDMA1_S0_X_COUNT	0xFFC01F50	/* MemDMA1 Stream 0 Source Inner-Loop Count */
#define MDMA1_S0_Y_COUNT	0xFFC01F58	/* MemDMA1 Stream 0 Source Outer-Loop Count */
#define MDMA1_S0_X_MODIFY	0xFFC01F54	/* MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
#define MDMA1_S0_Y_MODIFY	0xFFC01F5C	/* MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
#define MDMA1_S0_CURR_DESC_PTR	0xFFC01F60	/* MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
#define MDMA1_S0_CURR_ADDR	0xFFC01F64	/* MemDMA1 Stream 0 Source Current Address */
#define MDMA1_S0_CURR_X_COUNT	0xFFC01F70	/* MemDMA1 Stream 0 Source Current Inner-Loop Count */
#define MDMA1_S0_CURR_Y_COUNT `	0xFFC01F78	/* MemDMA1 Stream 0 Source Current Outer-Loop Count */
#define MDMA1_S0_IRQ_STATUS	0xFFC01F68	/* MemDMA1 Stream 0 Source Interrupt/Status */
#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C	/* MemDMA1 Stream 0 Source Peripheral Map */

#define MDMA1_D1_CONFIG		0xFFC01F88	/* MemDMA1 Stream 1 Destination Configuration */
#define MDMA1_D1_NEXT_DESC_PTR	0xFFC01F80	/* MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
#define MDMA1_D1_START_ADDR	0xFFC01F84	/* MemDMA1 Stream 1 Destination Start Address */
#define MDMA1_D1_X_COUNT	0xFFC01F90	/* MemDMA1 Stream 1 Destination Inner-Loop Count */
#define MDMA1_D1_Y_COUNT	0xFFC01F98	/* MemDMA1 Stream 1 Destination Outer-Loop Count */
#define MDMA1_D1_X_MODIFY	0xFFC01F94	/* MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
#define MDMA1_D1_Y_MODIFY	0xFFC01F9C	/* MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
#define MDMA1_D1_CURR_DESC_PTR	0xFFC01FA0	/* MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
#define MDMA1_D1_CURR_ADDR	0xFFC01FA4	/* MemDMA1 Stream 1 Dest Current Address */
#define MDMA1_D1_CURR_X_COUNT	0xFFC01FB0	/* MemDMA1 Stream 1 Dest Current Inner-Loop Count */
#define MDMA1_D1_CURR_Y_COUNT	0xFFC01FB8	/* MemDMA1 Stream 1 Dest Current Outer-Loop Count */
#define MDMA1_D1_IRQ_STATUS	0xFFC01FA8	/* MemDMA1 Stream 1 Dest Interrupt/Status */
#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC	/* MemDMA1 Stream 1 Dest Peripheral Map */

#define MDMA1_S1_CONFIG		0xFFC01FC8	/* MemDMA1 Stream 1 Source Configuration */
#define MDMA1_S1_NEXT_DESC_PTR	0xFFC01FC0	/* MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
#define MDMA1_S1_START_ADDR	0xFFC01FC4	/* MemDMA1 Stream 1 Source Start Address */
#define MDMA1_S1_X_COUNT	0xFFC01FD0	/* MemDMA1 Stream 1 Source Inner-Loop Count */
#define MDMA1_S1_Y_COUNT	0xFFC01FD8	/* MemDMA1 Stream 1 Source Outer-Loop Count */
#define MDMA1_S1_X_MODIFY	0xFFC01FD4	/* MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
#define MDMA1_S1_Y_MODIFY	0xFFC01FDC	/* MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
#define MDMA1_S1_CURR_DESC_PTR	0xFFC01FE0	/* MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
#define MDMA1_S1_CURR_ADDR	0xFFC01FE4	/* MemDMA1 Stream 1 Source Current Address */
#define MDMA1_S1_CURR_X_COUNT	0xFFC01FF0	/* MemDMA1 Stream 1 Source Current Inner-Loop Count */
#define MDMA1_S1_CURR_Y_COUNT	0xFFC01FF8	/* MemDMA1 Stream 1 Source Current Outer-Loop Count */
#define MDMA1_S1_IRQ_STATUS	0xFFC01FE8	/* MemDMA1 Stream 1 Source Interrupt/Status */
#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC	/* MemDMA1 Stream 1 Source Peripheral Map */

/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
#define DMA2_0_CONFIG		0xFFC00C08	/* DMA2 Channel 0 Configuration register */
#define DMA2_0_NEXT_DESC_PTR	0xFFC00C00	/* DMA2 Channel 0 Next Descripter Ptr Reg */
#define DMA2_0_START_ADDR	0xFFC00C04	/* DMA2 Channel 0 Start Address */
#define DMA2_0_X_COUNT		0xFFC00C10	/* DMA2 Channel 0 Inner Loop Count */
#define DMA2_0_Y_COUNT		0xFFC00C18	/* DMA2 Channel 0 Outer Loop Count */
#define DMA2_0_X_MODIFY		0xFFC00C14	/* DMA2 Channel 0 Inner Loop Addr Increment */
#define DMA2_0_Y_MODIFY		0xFFC00C1C	/* DMA2 Channel 0 Outer Loop Addr Increment */
#define DMA2_0_CURR_DESC_PTR	0xFFC00C20	/* DMA2 Channel 0 Current Descriptor Pointer */
#define DMA2_0_CURR_ADDR	0xFFC00C24	/* DMA2 Channel 0 Current Address Pointer */
#define DMA2_0_CURR_X_COUNT	0xFFC00C30	/* DMA2 Channel 0 Current Inner Loop Count */
#define DMA2_0_CURR_Y_COUNT	0xFFC00C38	/* DMA2 Channel 0 Current Outer Loop Count */
#define DMA2_0_IRQ_STATUS	0xFFC00C28	/* DMA2 Channel 0 Interrupt Status Register */
#define DMA2_0_PERIPHERAL_MAP	0xFFC00C2C	/* DMA2 Channel 0 Peripheral Map Register */

#define DMA2_1_CONFIG		0xFFC00C48	/* DMA2 Channel 1 Configuration register */
#define DMA2_1_NEXT_DESC_PTR	0xFFC00C40	/* DMA2 Channel 1 Next Descripter Ptr Reg */
#define DMA2_1_START_ADDR	0xFFC00C44	/* DMA2 Channel 1 Start Address */
#define DMA2_1_X_COUNT		0xFFC00C50	/* DMA2 Channel 1 Inner Loop Count */
#define DMA2_1_Y_COUNT		0xFFC00C58	/* DMA2 Channel 1 Outer Loop Count */
#define DMA2_1_X_MODIFY		0xFFC00C54	/* DMA2 Channel 1 Inner Loop Addr Increment */
#define DMA2_1_Y_MODIFY		0xFFC00C5C	/* DMA2 Channel 1 Outer Loop Addr Increment */
#define DMA2_1_CURR_DESC_PTR	0xFFC00C60	/* DMA2 Channel 1 Current Descriptor Pointer */
#define DMA2_1_CURR_ADDR	0xFFC00C64	/* DMA2 Channel 1 Current Address Pointer */
#define DMA2_1_CURR_X_COUNT	0xFFC00C70	/* DMA2 Channel 1 Current Inner Loop Count */
#define DMA2_1_CURR_Y_COUNT	0xFFC00C78	/* DMA2 Channel 1 Current Outer Loop Count */
#define DMA2_1_IRQ_STATUS	0xFFC00C68	/* DMA2 Channel 1 Interrupt Status Register */
#define DMA2_1_PERIPHERAL_MAP	0xFFC00C6C	/* DMA2 Channel 1 Peripheral Map Register */

#define DMA2_2_CONFIG		0xFFC00C88	/* DMA2 Channel 2 Configuration register */
#define DMA2_2_NEXT_DESC_PTR	0xFFC00C80	/* DMA2 Channel 2 Next Descripter Ptr Reg */
#define DMA2_2_START_ADDR	0xFFC00C84	/* DMA2 Channel 2 Start Address */
#define DMA2_2_X_COUNT		0xFFC00C90	/* DMA2 Channel 2 Inner Loop Count */
#define DMA2_2_Y_COUNT		0xFFC00C98	/* DMA2 Channel 2 Outer Loop Count */
#define DMA2_2_X_MODIFY		0xFFC00C94	/* DMA2 Channel 2 Inner Loop Addr Increment */
#define DMA2_2_Y_MODIFY		0xFFC00C9C	/* DMA2 Channel 2 Outer Loop Addr Increment */
#define DMA2_2_CURR_DESC_PTR	0xFFC00CA0	/* DMA2 Channel 2 Current Descriptor Pointer */
#define DMA2_2_CURR_ADDR	0xFFC00CA4	/* DMA2 Channel 2 Current Address Pointer */
#define DMA2_2_CURR_X_COUNT	0xFFC00CB0	/* DMA2 Channel 2 Current Inner Loop Count */
#define DMA2_2_CURR_Y_COUNT	0xFFC00CB8	/* DMA2 Channel 2 Current Outer Loop Count */
#define DMA2_2_IRQ_STATUS	0xFFC00CA8	/* DMA2 Channel 2 Interrupt Status Register */
#define DMA2_2_PERIPHERAL_MAP	0xFFC00CAC	/* DMA2 Channel 2 Peripheral Map Register */

#define DMA2_3_CONFIG		0xFFC00CC8	/* DMA2 Channel 3 Configuration register */
#define DMA2_3_NEXT_DESC_PTR	0xFFC00CC0	/* DMA2 Channel 3 Next Descripter Ptr Reg */
#define DMA2_3_START_ADDR	0xFFC00CC4	/* DMA2 Channel 3 Start Address */
#define DMA2_3_X_COUNT		0xFFC00CD0	/* DMA2 Channel 3 Inner Loop Count */
#define DMA2_3_Y_COUNT		0xFFC00CD8	/* DMA2 Channel 3 Outer Loop Count */
#define DMA2_3_X_MODIFY		0xFFC00CD4	/* DMA2 Channel 3 Inner Loop Addr Increment */
#define DMA2_3_Y_MODIFY		0xFFC00CDC	/* DMA2 Channel 3 Outer Loop Addr Increment */
#define DMA2_3_CURR_DESC_PTR	0xFFC00CE0	/* DMA2 Channel 3 Current Descriptor Pointer */
#define DMA2_3_CURR_ADDR	0xFFC00CE4	/* DMA2 Channel 3 Current Address Pointer */
#define DMA2_3_CURR_X_COUNT	0xFFC00CF0	/* DMA2 Channel 3 Current Inner Loop Count */
#define DMA2_3_CURR_Y_COUNT	0xFFC00CF8	/* DMA2 Channel 3 Current Outer Loop Count */
#define DMA2_3_IRQ_STATUS	0xFFC00CE8	/* DMA2 Channel 3 Interrupt Status Register */
#define DMA2_3_PERIPHERAL_MAP	0xFFC00CEC	/* DMA2 Channel 3 Peripheral Map Register */

#define DMA2_4_CONFIG		0xFFC00D08	/* DMA2 Channel 4 Configuration register */
#define DMA2_4_NEXT_DESC_PTR	0xFFC00D00	/* DMA2 Channel 4 Next Descripter Ptr Reg */
#define DMA2_4_START_ADDR	0xFFC00D04	/* DMA2 Channel 4 Start Address */
#define DMA2_4_X_COUNT		0xFFC00D10	/* DMA2 Channel 4 Inner Loop Count */
#define DMA2_4_Y_COUNT		0xFFC00D18	/* DMA2 Channel 4 Outer Loop Count */
#define DMA2_4_X_MODIFY		0xFFC00D14	/* DMA2 Channel 4 Inner Loop Addr Increment */
#define DMA2_4_Y_MODIFY		0xFFC00D1C	/* DMA2 Channel 4 Outer Loop Addr Increment */
#define DMA2_4_CURR_DESC_PTR	0xFFC00D20	/* DMA2 Channel 4 Current Descriptor Pointer */
#define DMA2_4_CURR_ADDR	0xFFC00D24	/* DMA2 Channel 4 Current Address Pointer */
#define DMA2_4_CURR_X_COUNT	0xFFC00D30	/* DMA2 Channel 4 Current Inner Loop Count */
#define DMA2_4_CURR_Y_COUNT	0xFFC00D38	/* DMA2 Channel 4 Current Outer Loop Count */
#define DMA2_4_IRQ_STATUS	0xFFC00D28	/* DMA2 Channel 4 Interrupt Status Register */
#define DMA2_4_PERIPHERAL_MAP	0xFFC00D2C	/* DMA2 Channel 4 Peripheral Map Register */

#define DMA2_5_CONFIG		0xFFC00D48	/* DMA2 Channel 5 Configuration register */
#define DMA2_5_NEXT_DESC_PTR	0xFFC00D40	/* DMA2 Channel 5 Next Descripter Ptr Reg */
#define DMA2_5_START_ADDR	0xFFC00D44	/* DMA2 Channel 5 Start Address */
#define DMA2_5_X_COUNT		0xFFC00D50	/* DMA2 Channel 5 Inner Loop Count */
#define DMA2_5_Y_COUNT		0xFFC00D58	/* DMA2 Channel 5 Outer Loop Count */
#define DMA2_5_X_MODIFY		0xFFC00D54	/* DMA2 Channel 5 Inner Loop Addr Increment */
#define DMA2_5_Y_MODIFY		0xFFC00D5C	/* DMA2 Channel 5 Outer Loop Addr Increment */
#define DMA2_5_CURR_DESC_PTR	0xFFC00D60	/* DMA2 Channel 5 Current Descriptor Pointer */
#define DMA2_5_CURR_ADDR	0xFFC00D64	/* DMA2 Channel 5 Current Address Pointer */
#define DMA2_5_CURR_X_COUNT	0xFFC00D70	/* DMA2 Channel 5 Current Inner Loop Count */
#define DMA2_5_CURR_Y_COUNT	0xFFC00D78	/* DMA2 Channel 5 Current Outer Loop Count */
#define DMA2_5_IRQ_STATUS	0xFFC00D68	/* DMA2 Channel 5 Interrupt Status Register */
#define DMA2_5_PERIPHERAL_MAP	0xFFC00D6C	/* DMA2 Channel 5 Peripheral Map Register */

#define DMA2_6_CONFIG		0xFFC00D88	/* DMA2 Channel 6 Configuration register */
#define DMA2_6_NEXT_DESC_PTR	0xFFC00D80	/* DMA2 Channel 6 Next Descripter Ptr Reg */
#define DMA2_6_START_ADDR	0xFFC00D84	/* DMA2 Channel 6 Start Address */
#define DMA2_6_X_COUNT		0xFFC00D90	/* DMA2 Channel 6 Inner Loop Count */
#define DMA2_6_Y_COUNT		0xFFC00D98	/* DMA2 Channel 6 Outer Loop Count */
#define DMA2_6_X_MODIFY		0xFFC00D94	/* DMA2 Channel 6 Inner Loop Addr Increment */
#define DMA2_6_Y_MODIFY		0xFFC00D9C	/* DMA2 Channel 6 Outer Loop Addr Increment */
#define DMA2_6_CURR_DESC_PTR	0xFFC00DA0	/* DMA2 Channel 6 Current Descriptor Pointer */
#define DMA2_6_CURR_ADDR	0xFFC00DA4	/* DMA2 Channel 6 Current Address Pointer */
#define DMA2_6_CURR_X_COUNT	0xFFC00DB0	/* DMA2 Channel 6 Current Inner Loop Count */
#define DMA2_6_CURR_Y_COUNT	0xFFC00DB8	/* DMA2 Channel 6 Current Outer Loop Count */
#define DMA2_6_IRQ_STATUS	0xFFC00DA8	/* DMA2 Channel 6 Interrupt Status Register */
#define DMA2_6_PERIPHERAL_MAP	0xFFC00DAC	/* DMA2 Channel 6 Peripheral Map Register */

#define DMA2_7_CONFIG		0xFFC00DC8	/* DMA2 Channel 7 Configuration register */