defbf561.h

u-boot1.3.0的原码,从配了网络驱动和FLASH的驱动,并该用ESC竟如

/*
 * defBF561.h
 *
 * (c) Copyright 2001-2003 Analog Devices, Inc.  All rights reserved.
 *
 */

/* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */

#ifndef _DEF_BF561_H
#define _DEF_BF561_H

/*
 * #if !defined(__ADSPBF561__)
 * #warning defBF561.h should only be included for BF561 chip.
 * #endif
 */

/* include all Core registers and bit definitions */
#include <asm/arch-common/def_LPBlackfin.h>

/*
 * Helper macros
 * usage:
 * P0.H = HI(UART_THR);
 * P0.L = LO(UART_THR);
 */

#define LO(con32) ((con32) & 0xFFFF)
#define lo(con32) ((con32) & 0xFFFF)
#define HI(con32) (((con32) >> 16) & 0xFFFF)
#define hi(con32) (((con32) >> 16) & 0xFFFF)

/*
 * System MMR Register Map
 */

/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define PLL_CTL			0xFFC00000	/* PLL Control register */
#define PLL_DIV			0xFFC00004	/* PLL Divide Register */
#define VR_CTL			0xFFC00008	/* Voltage Regulator Control Register */
#define PLL_STAT		0xFFC0000C	/* PLL Status register */
#define PLL_LOCKCNT		0xFFC00010	/* PLL Lock Count register */

/*
 * System Reset and Interrupt Controller registers for
 * core A (0xFFC0 0100-0xFFC0 01FF)
 */
#define SICA_SWRST		0xFFC00100	/* Software Reset register */
#define SICA_SYSCR		0xFFC00104	/* System Reset Configuration register */
#define SICA_RVECT		0xFFC00108	/* SIC Reset Vector Address Register */
#define SICA_IMASK		0xFFC0010C	/* SIC Interrupt Mask register 0 */
#define SICA_IMASK0		0xFFC0010C	/* SIC Interrupt Mask register 0 */
#define SICA_IMASK1		0xFFC00110	/* SIC Interrupt Mask register 1 */
#define SICA_IAR0		0xFFC00124	/* SIC Interrupt Assignment Register 0 */
#define SICA_IAR1		0xFFC00128	/* SIC Interrupt Assignment Register 1 */
#define SICA_IAR2		0xFFC0012C	/* SIC Interrupt Assignment Register 2 */
#define SICA_IAR3		0xFFC00130	/* SIC Interrupt Assignment Register 3 */
#define SICA_IAR4		0xFFC00134	/* SIC Interrupt Assignment Register 4 */
#define SICA_IAR5		0xFFC00138	/* SIC Interrupt Assignment Register 5 */
#define SICA_IAR6		0xFFC0013C	/* SIC Interrupt Assignment Register 6 */
#define SICA_IAR7		0xFFC00140	/* SIC Interrupt Assignment Register 7 */
#define SICA_ISR0		0xFFC00114	/* SIC Interrupt Status register 0 */
#define SICA_ISR1		0xFFC00118	/* SIC Interrupt Status register 1 */
#define SICA_IWR0		0xFFC0011C	/* SIC Interrupt Wakeup-Enable register 0 */
#define SICA_IWR1		0xFFC00120	/* SIC Interrupt Wakeup-Enable register 1 */

/*
 * System Reset and Interrupt Controller registers for
 * Core B (0xFFC0 1100-0xFFC0 11FF)
 */
#define SICB_SWRST		0xFFC01100	/* reserved */
#define SICB_SYSCR		0xFFC01104	/* reserved */
#define SICB_RVECT		0xFFC01108	/* SIC Reset Vector Address Register */
#define SICB_IMASK0		0xFFC0110C	/* SIC Interrupt Mask register 0 */
#define SICB_IMASK1		0xFFC01110	/* SIC Interrupt Mask register 1 */
#define SICB_IAR0		0xFFC01124	/* SIC Interrupt Assignment Register 0 */
#define SICB_IAR1		0xFFC01128	/* SIC Interrupt Assignment Register 1 */
#define SICB_IAR2		0xFFC0112C	/* SIC Interrupt Assignment Register 2 */
#define SICB_IAR3		0xFFC01130	/* SIC Interrupt Assignment Register 3 */
#define SICB_IAR4		0xFFC01134	/* SIC Interrupt Assignment Register 4 */
#define SICB_IAR5		0xFFC01138	/* SIC Interrupt Assignment Register 5 */
#define SICB_IAR6		0xFFC0113C	/* SIC Interrupt Assignment Register 6 */
#define SICB_IAR7		0xFFC01140	/* SIC Interrupt Assignment Register 7 */
#define SICB_ISR0		0xFFC01114	/* SIC Interrupt Status register 0 */
#define SICB_ISR1		0xFFC01118	/* SIC Interrupt Status register 1 */
#define SICB_IWR0		0xFFC0111C	/* SIC Interrupt Wakeup-Enable register 0 */
#define SICB_IWR1		0xFFC01120	/* SIC Interrupt Wakeup-Enable register 1 */

/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
#define WDOGA_CTL		0xFFC00200	/* Watchdog Control register */
#define WDOGA_CNT		0xFFC00204	/* Watchdog Count register */
#define WDOGA_STAT		0xFFC00208	/* Watchdog Status register */

/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
#define WDOGB_CTL		0xFFC01200	/* Watchdog Control register */
#define WDOGB_CNT		0xFFC01204	/* Watchdog Count register */
#define WDOGB_STAT		0xFFC01208	/* Watchdog Status register */

/* UART Controller (0xFFC00400 - 0xFFC004FF) */
#define UART_THR		0xFFC00400	/* Transmit Holding register */
#define UART_RBR		0xFFC00400	/* Receive Buffer register */
#define UART_DLL		0xFFC00400	/* Divisor Latch (Low-Byte) */
#define UART_IER		0xFFC00404	/* Interrupt Enable Register */
#define UART_DLH		0xFFC00404	/* Divisor Latch (High-Byte) */
#define UART_IIR		0xFFC00408	/* Interrupt Identification Register */
#define UART_LCR		0xFFC0040C	/* Line Control Register */
#define UART_MCR		0xFFC00410	/* Modem Control Register */
#define UART_LSR		0xFFC00414	/* Line Status Register */
#define UART_MSR		0xFFC00418	/* Modem Status Register */
#define UART_SCR		0xFFC0041C	/* SCR Scratch Register */
#define UART_GCTL		0xFFC00424	/* Global Control Register */

/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI_CTL			0xFFC00500	/* SPI Control Register */
#define SPI_FLG			0xFFC00504	/* SPI Flag register */
#define SPI_STAT		0xFFC00508	/* SPI Status register */
#define SPI_TDBR		0xFFC0050C	/* SPI Transmit Data Buffer Register */
#define SPI_RDBR		0xFFC00510	/* SPI Receive Data Buffer Register */
#define SPI_BAUD		0xFFC00514	/* SPI Baud rate Register */
#define SPI_SHADOW		0xFFC00518	/* SPI_RDBR Shadow Register */

/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
#define TIMER0_CONFIG		0xFFC00600	/* Timer0 Configuration register */
#define TIMER0_COUNTER		0xFFC00604	/* Timer0 Counter register */
#define TIMER0_PERIOD		0xFFC00608	/* Timer0 Period register */
#define TIMER0_WIDTH		0xFFC0060C	/* Timer0 Width register */
#define TIMER1_CONFIG		0xFFC00610	/* Timer1 Configuration register */
#define TIMER1_COUNTER		0xFFC00614	/* Timer1 Counter register */
#define TIMER1_PERIOD		0xFFC00618	/* Timer1 Period register */
#define TIMER1_WIDTH		0xFFC0061C	/* Timer1 Width register */
#define TIMER2_CONFIG		0xFFC00620	/* Timer2 Configuration register */
#define TIMER2_COUNTER		0xFFC00624	/* Timer2 Counter register */
#define TIMER2_PERIOD		0xFFC00628	/* Timer2 Period register */
#define TIMER2_WIDTH		0xFFC0062C	/* Timer2 Width register */
#define TIMER3_CONFIG		0xFFC00630	/* Timer3 Configuration register */
#define TIMER3_COUNTER		0xFFC00634	/* Timer3 Counter register */
#define TIMER3_PERIOD		0xFFC00638	/* Timer3 Period register */
#define TIMER3_WIDTH		0xFFC0063C	/* Timer3 Width register */
#define TIMER4_CONFIG		0xFFC00640	/* Timer4 Configuration register */
#define TIMER4_COUNTER		0xFFC00644	/* Timer4 Counter register */
#define TIMER4_PERIOD		0xFFC00648	/* Timer4 Period register */
#define TIMER4_WIDTH		0xFFC0064C	/* Timer4 Width register */
#define TIMER5_CONFIG		0xFFC00650	/* Timer5 Configuration register */
#define TIMER5_COUNTER		0xFFC00654	/* Timer5 Counter register */
#define TIMER5_PERIOD		0xFFC00658	/* Timer5 Period register */
#define TIMER5_WIDTH		0xFFC0065C	/* Timer5 Width register */
#define TIMER6_CONFIG		0xFFC00660	/* Timer6 Configuration register */
#define TIMER6_COUNTER		0xFFC00664	/* Timer6 Counter register */
#define TIMER6_PERIOD		0xFFC00668	/* Timer6 Period register */
#define TIMER6_WIDTH		0xFFC0066C	/* Timer6 Width register */
#define TIMER7_CONFIG		0xFFC00670	/* Timer7 Configuration register */
#define TIMER7_COUNTER		0xFFC00674	/* Timer7 Counter register */
#define TIMER7_PERIOD		0xFFC00678	/* Timer7 Period register */
#define TIMER7_WIDTH		0xFFC0067C	/* Timer7 Width register */
#define TMRS8_ENABLE		0xFFC00680	/* Timer Enable Register */
#define TMRS8_DISABLE		0xFFC00684	/* Timer Disable register */
#define TMRS8_STATUS		0xFFC00688	/* Timer Status register */

/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
#define TIMER8_CONFIG		0xFFC01600	/* Timer8 Configuration register */
#define TIMER8_COUNTER		0xFFC01604	/* Timer8 Counter register */
#define TIMER8_PERIOD		0xFFC01608	/* Timer8 Period register */
#define TIMER8_WIDTH		0xFFC0160C	/* Timer8 Width register */
#define TIMER9_CONFIG		0xFFC01610	/* Timer9 Configuration register */
#define TIMER9_COUNTER		0xFFC01614	/* Timer9 Counter register */
#define TIMER9_PERIOD		0xFFC01618	/* Timer9 Period register */
#define TIMER9_WIDTH		0xFFC0161C	/* Timer9 Width register */
#define TIMER10_CONFIG		0xFFC01620	/* Timer10 Configuration register */
#define TIMER10_COUNTER		0xFFC01624	/* Timer10 Counter register */
#define TIMER10_PERIOD		0xFFC01628	/* Timer10 Period register */
#define TIMER10_WIDTH		0xFFC0162C	/* Timer10 Width register */
#define TIMER11_CONFIG		0xFFC01630	/* Timer11 Configuration register */
#define TIMER11_COUNTER		0xFFC01634	/* Timer11 Counter register */
#define TIMER11_PERIOD		0xFFC01638	/* Timer11 Period register */
#define TIMER11_WIDTH		0xFFC0163C	/* Timer11 Width register */
#define TMRS4_ENABLE		0xFFC01640	/* Timer Enable Register */
#define TMRS4_DISABLE		0xFFC01644	/* Timer Disable register */
#define TMRS4_STATUS		0xFFC01648	/* Timer Status register */

/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
#define FIO0_FLAG_D		0xFFC00700	/* Flag Data register */
#define FIO0_FLAG_C		0xFFC00704	/* Flag Clear register */
#define FIO0_FLAG_S		0xFFC00708	/* Flag Set register */
#define FIO0_FLAG_T		0xFFC0070C	/* Flag Toggle register */
#define FIO0_MASKA_D		0xFFC00710	/* Flag Mask Interrupt A Data register */
#define FIO0_MASKA_C		0xFFC00714	/* Flag Mask Interrupt A Clear register */
#define FIO0_MASKA_S		0xFFC00718	/* Flag Mask Interrupt A Set register */
#define FIO0_MASKA_T		0xFFC0071C	/* Flag Mask Interrupt A Toggle register */
#define FIO0_MASKB_D		0xFFC00720	/* Flag Mask Interrupt B Data register */
#define FIO0_MASKB_C		0xFFC00724	/* Flag Mask Interrupt B Clear register */
#define FIO0_MASKB_S		0xFFC00728	/* Flag Mask Interrupt B Set register */
#define FIO0_MASKB_T		0xFFC0072C	/* Flag Mask Interrupt B Toggle register */
#define FIO0_DIR		0xFFC00730	/* Flag Direction  register */
#define FIO0_POLAR		0xFFC00734	/* Flag Polarity register */
#define FIO0_EDGE		0xFFC00738	/* Flag Interrupt Sensitivity register */
#define FIO0_BOTH		0xFFC0073C	/* Flag Set on Both Edges register */
#define FIO0_INEN		0xFFC00740	/* Flag Input Enable register */

/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
#define FIO1_FLAG_D		0xFFC01500	/* Flag Data register */
#define FIO1_FLAG_C		0xFFC01504	/* Flag Clear register */
#define FIO1_FLAG_S		0xFFC01508	/* Flag Set register */
#define FIO1_FLAG_T		0xFFC0150C	/* Flag Toggle register */
#define FIO1_MASKA_D		0xFFC01510	/* Flag Mask Interrupt A Data register */
#define FIO1_MASKA_C		0xFFC01514	/* Flag Mask Interrupt A Clear register */
#define FIO1_MASKA_S		0xFFC01518	/* Flag Mask Interrupt A Set register */
#define FIO1_MASKA_T		0xFFC0151C	/* Flag Mask Interrupt A Toggle register */
#define FIO1_MASKB_D		0xFFC01520	/* Flag Mask Interrupt B Data register */
#define FIO1_MASKB_C		0xFFC01524	/* Flag Mask Interrupt B Clear register */
#define FIO1_MASKB_S		0xFFC01528	/* Flag Mask Interrupt B Set register */
#define FIO1_MASKB_T		0xFFC0152C	/* Flag Mask Interrupt B Toggle register */
#define FIO1_DIR		0xFFC01530	/* Flag Direction register */
#define FIO1_POLAR		0xFFC01534	/* Flag Polarity register */