boot.s

Show hou use semaphores in RTL-ARM

	/* Sample initialization file */

	.extern main
	.extern exit

	.text
	.code 32


	.align  0

	.extern __bss_start
	.extern __bss_end__
	.extern _top_stack_
	.extern _data
	.extern _edata
	.extern __data+beg_src__

	.global start
	.global endless_loop
	.global _app_entry

	/* Stack Sizes */
    .set  UND_STACK_SIZE, 0x00000004
    .set  ABT_STACK_SIZE, 0x00000004
    .set  FIQ_STACK_SIZE, 0x00000004
    .set  IRQ_STACK_SIZE, 0X00000900
    .set  SVC_STACK_SIZE, 0x00000900

	/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
    .set  MODE_USR, 0x10            /* User Mode */
    .set  MODE_FIQ, 0x11            /* FIQ Mode */
    .set  MODE_IRQ, 0x12            /* IRQ Mode */
    .set  MODE_SVC, 0x13            /* Supervisor Mode */
    .set  MODE_ABT, 0x17            /* Abort Mode */
    .set  MODE_UND, 0x1B            /* Undefined Mode */
    .set  MODE_SYS, 0x1F            /* System Mode */

    .equ  I_BIT, 0x80               /* when I bit is set, IRQ is disabled */
    .equ  F_BIT, 0x40               /* when F bit is set, FIQ is disabled */

# system control block
		.equ	SCB_BASE,			0xE01FC000

		.equ	SCBOFF_EXTINT,		0x140
		.equ	SCBOFF_EXTMODE,		0x148
		.equ	SCBOFF_EXTPOLAR,	0x14C
		.equ	SCBOFF_RSID,		0x180
		.equ	SCBOFF_CSPR,		0x184
		.equ	SCBOFF_AHBCFG1,		0x188
		.equ	SCBOFF_AHBCFG2,		0x18C
		.equ	SCBOFF_SCS,			0x1A0
		
		.equ	SCBOFF_CLKSRCSEL,	0x10C
		.equ	SCBOFF_PLLCON,		0x080
		.equ	SCBOFF_PLLCFG,		0x084
		.equ	SCBOFF_PLLSTAT,		0x088
		.equ	SCBOFF_PLLFEED,		0x08C
		
		.equ	SCBOFF_CCLKCFG,		0x104
		.equ	SCBOFF_USBCLKCFG,	0x108	
		.equ	SCBOFF_APBDIV,		0x100
		.equ	SCBOFF_PCLKSEL0,	0x1A8
		.equ	SCBOFF_PCLKSEL1,	0x1AC
		
		.equ	SCBOFF_PCON,		0x0C0
		.equ	SCBOFF_INTWAKE,		0x144
		.equ	SCBOFF_PCONP,		0x0C4


start:
_start:
_mainCRTStartup:
Hard_Reset:  
_app_entry:

	/* Setup a stack for each mode - note that this only sets up a usable stack
	for system/user, SWI and IRQ modes.   Also each mode is setup with
	interrupts initially disabled. */
    ldr   r0, .LC6
    msr   CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode
    mov   sp, r0
    sub   r0, r0, #UND_STACK_SIZE
    msr   CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
    mov   sp, r0
    sub   r0, r0, #ABT_STACK_SIZE
    msr   CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
    mov   sp, r0
    sub   r0, r0, #FIQ_STACK_SIZE
    msr   CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
    mov   sp, r0
    sub   r0, r0, #IRQ_STACK_SIZE
    msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
    mov   sp, r0
    sub   r0, r0, #SVC_STACK_SIZE
    msr   CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
    mov   sp, r0

	/* We want to start in supervisor mode.  Operation will switch to system
	mode when the first task starts. */
	msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT

	/* Clear BSS. */

	mov     a2, #0			/* Fill value */
	mov		fp, a2			/* Null frame pointer */
	mov		r7, a2			/* Null frame pointer for Thumb */

	ldr		r1, .LC1		/* Start of memory block */
	ldr		r3, .LC2		/* End of memory block */
	subs	r3, r3, r1      /* Length of block */
	beq		.end_clear_loop
	mov		r2, #0

.clear_loop:
	strb	r2, [r1], #1
	subs	r3, r3, #1
	bgt		.clear_loop

.end_clear_loop:

	/* Initialise data. */

	ldr		r1, .LC3		/* Start of memory block */
	ldr		r2, .LC4		/* End of memory block */
	ldr		r3, .LC5
	subs	r3, r3, r1		/* Length of block */
	beq		.end_set_loop

.set_loop:
	ldrb	r4, [r2], #1
	strb	r4, [r1], #1
	subs	r3, r3, #1
	bgt		.set_loop

# Setup Clock and PLL
		.equ	SCS_Val,      	0x00000020
		.equ	CLKSRCSEL_Val,  0x00000001
		.equ	PLLCFG_Val,     0x0000000D
		.equ	CCLKCFG_Val,    0x00000006
		.equ	USBCLKCFG_Val,  0x00000000
		.equ	PCLKSEL0_Val,   0x00000000
		.equ	PCLKSEL1_Val,   0x00000000

		.equ 	PLLSTAT_M,		0x00007FFF 		/* PLL M Value */
		.equ	PLLSTAT_N,      0x00FF0000     	/* PLL N Value */
		.equ	PLLSTAT_PLOCK,  0x04000000      /* PLL Lock Status */

        ldr     r0, =SCB_BASE
        mov     r1, #0xAA
        mov     r2, #0x55

#  Configure and Enable PLL
        ldr     r3, =SCS_Val          			/* Enable main oscillator 		*/
        str     r3, [r0, #SCBOFF_SCS] 

		ldr 	r4,	=SCS_Val
OSC:
        ldr     r3, [r0, #SCBOFF_SCS]	   		/* Wait for main osc stabilize 	*/
        and		r3, r3, r4
        cmp		r3, r4
        bne     OSC

        ldr     r3, =CLKSRCSEL_Val				/* Select PLL source clock 	*/
        str     r3, [r0, #SCBOFF_CLKSRCSEL] 
        ldr  	r3, =PLLCFG_Val					/* PLL Config				*/
        str     r3, [r0, #SCBOFF_PLLCFG] 
        str     r1, [r0, #SCBOFF_PLLFEED]
        str     r2, [r0, #SCBOFF_PLLFEED]
        
        mov     r3, #0x01						/* enable PLL				*/
        str     r3, [r0, #SCBOFF_PLLCON]
        str     r1, [r0, #SCBOFF_PLLFEED]
		str     r2, [r0, #SCBOFF_PLLFEED]

#  Wait until PLL Locked
		ldr 	r4, =PLLSTAT_PLOCK 
LoopPLL:
		ldr     R3, [r0, #SCBOFF_PLLSTAT]
		and		r3,	r3, r4
		cmp     r3, r4
		bne     LoopPLL

MN_Lock:
        ldr     r3, [r0, #SCBOFF_PLLSTAT]
        ldr     r4, =(PLLSTAT_M | PLLSTAT_N)
        and     r3, r3, r4
        ldr     r4, =PLLCFG_Val					/* PLL Config value 		*/
        eors    r3, r3, r4
        bne     MN_Lock

# Setup CPU clock divider
# main clock is 12Mhz now divided by 6
        mov     r3, #CCLKCFG_Val				/* clock config value		*/
        str     r3, [r0, #SCBOFF_CCLKCFG]

# Setup Peripheral Clock
        mov     r3, #PCLKSEL0_Val				/* clock selector value 0	*/
        str     r3, [r0, #SCBOFF_PCLKSEL0]
        ldr     r3, =PCLKSEL1_Val				/* clock selector value 1	*/
        str     r3, [r0, #SCBOFF_PCLKSEL1]

# Switch to PLL Clock
# PLL clock is 2 x 12 x 12 / 6 --> 48 MHz 
        mov     r3, #0x03					    /* PLL enable & connect		*/
        str     r3, [r0, #SCBOFF_PLLCON]
        str     r1, [r0, #SCBOFF_PLLFEED]
        str     r2, [r0, #SCBOFF_PLLFEED]

# Peripheral clock divider  
        .equ    APBDIV,     	0xE01FC100

# Setup APDDIV	
        ldr     R0, =APBDIV
        ldr     R1, =0x00
        str     R1, [R0]

# Memory Accelerator Module (MAM) definitions
		.equ	MAM_BASE, 		 	0xE01FC000      /* MAM Base Address   */
		.equ	MAMCR_OFS,			0x00            /* MAM Control Offset */ 
		.equ	MAMTIM_OFS,			0x04            /* MAM Timing Offset  */

# setup memory accelerator

		.equ	MAMCR_Val,    0x00000002
		.equ	MAMTIM_Val,   0x00000004

        ldr     r0, =MAM_BASE
        mov     r1, #MAMTIM_Val
        str     r1, [r0, #MAMTIM_OFS] 
        mov     r1, #MAMCR_Val
        str     r1, [r0, #MAMCR_OFS] 

.end_set_loop:

	mov		r0, #0          /* no arguments  */
	mov		r1, #0          /* no argv either */

	bl		main

endless_loop:
	b               endless_loop


	.align 0

	.LC1:
	.word   __bss_start
	.LC2:
	.word   __bss_end__
	.LC3:
	.word   _data
	.LC4:
	.word   __data_beg_src__
	.LC5:
	.word   _edata
	.LC6:
	.word   _top_stack_


	/* Setup vector table.  Note that undf, pabt, dabt, fiq just execute
	a null loop. */

.section .startup,"ax"
         .code 32
         .align 0

	b     _start						/* reset - _start			*/
	ldr   pc, _undf						/* undefined - _undf		*/
	ldr   pc, _swi						/* SWI - _swi				*/
	ldr   pc, _pabt						/* program abort - _pabt	*/
	ldr   pc, _dabt						/* data abort - _dabt		*/
	nop									/* reserved					*/
	ldr   pc, [PC, #-0x120]				/* IRQ - read the VIC		*/
	ldr   pc, _fiq						/* FIQ - _fiq				*/

_undf:  .word __undf                    /* undefined				*/
_swi:   .word vPortYieldProcessor       /* SWI						*/
_pabt:  .word __pabt                    /* program abort			*/
_dabt:  .word __dabt                    /* data abort				*/
_fiq:   .word __fiq                     /* FIQ						*/

__undf: b     .                         /* undefined				*/
__pabt: b     .                         /* program abort			*/
__dabt: b     .                         /* data abort				*/
__fiq:  b     .                         /* FIQ						*/